From 022a81c44e655a9f81e974e730c0cecc1f048781 Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Fri, 9 Aug 2013 16:07:07 -0700 Subject: [PATCH] exynos5420: enable DMC internal clock gating lets enable memory controller internal clock gating for ddr3. with these bits enabled we save some power out of ddr3. This is ported from https://gerrit.chromium.org/gerrit/#/c/60774 Signed-off-by: David Hendricks BUG=none BRANCH=none TEST=built and booted on pit Change-Id: I2f9b0d78483b3ea7441f54a715c7c1e42eda3f7f Reviewed-on: https://gerrit.chromium.org/gerrit/65728 Reviewed-by: Ronald G. Minnich Commit-Queue: David Hendricks Tested-by: David Hendricks --- src/cpu/samsung/exynos5420/dmc_init_ddr3.c | 8 ++++++++ src/cpu/samsung/exynos5420/setup.h | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c index ebfe1e1a0f..6c431f374f 100644 --- a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c +++ b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c @@ -376,5 +376,13 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), &drex1->concontrol); + + /* Enable Clock Gating Control for DMC + * this saves around 25 mw dmc power as compared to the power + * consumption without these bits enabled + */ + setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG); + setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG); + return 0; } diff --git a/src/cpu/samsung/exynos5420/setup.h b/src/cpu/samsung/exynos5420/setup.h index 794d4e14df..8f14a91602 100644 --- a/src/cpu/samsung/exynos5420/setup.h +++ b/src/cpu/samsung/exynos5420/setup.h @@ -791,6 +791,14 @@ struct exynos5_phy_control; #define BRBRSVCONTROL_VAL 0x00000033 #define BRBRSVCONFIG_VAL 0x88778877 +/* Clock Gating Control (CGCONTROL) register */ +#define MEMIF_CG_EN (1 << 3) /* Memory interface clock gating */ +#define SCG_CG_EN (1 << 2) /* Scheduler clock gating */ +#define BUSIF_WR_CG_EN (1 << 1) /* Bus interface write channel clock gating */ +#define BUSIF_RD_CG_EN (1 << 0) /* Bus interface read channel clock gating */ +#define DMC_INTERNAL_CG (MEMIF_CG_EN | SCG_CG_EN | \ + BUSIF_WR_CG_EN | BUSIF_RD_CG_EN) + /* DMC PHY Control0 register */ #define PHY_CONTROL0_RESET_VAL 0x0 #define MEM_TERM_EN (1 << 31) /* Termination enable for memory */