ba3f529681
According to QEMU docs/specs/fw_cfg.rst, the selector and data register offsets of Arm & RISCV should be 0x8 and 0x0. Besides, the selector register should be in big-endian when using MMIO access. TEST=build and run successfully on QEMU rvvirt machine. Using command "qemu-system-riscv64 -machine virt -bios build/coreboot.rom -nographic -drive if=pflash,file=./build/coreboot.rom,format=raw". Change-Id: I1c4d40a4dbcac4067a7c69ba916e6ff0a21cdcb6 Signed-off-by: Dong Wei <weidong.wd@bytedance.com> Signed-off-by: Ziang Wang <wangziang.ok@bytedance.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> |
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| .. | ||
| bochs.c | ||
| cirrus.c | ||
| fw_cfg.c | ||
| Kconfig | ||
| Makefile.mk | ||
| qemu_debugcon.c | ||