Sean Rhodes fe14d96b80 soc/intel/cnvw: Add GPEH Method ... Add a general purpose handle to allow CNVi to be notified of state changes. Intel document #559910 details this. Change-Id: I36c98c525c99fb2b7b5ebd8b0e392e6626e97290 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83710 Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2024-10-11 08:32:04 +00:00
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amd	soc/amd/common/psp: add and call PSP SMI SPI RPMC function stubs	2024-10-09 18:18:19 +00:00
cavium	soc/cavium: Fix non matching types	2024-08-30 07:34:47 +00:00
example/min86	soc: Add SPDX license headers to Kconfig files	2024-02-18 02:03:37 +00:00
ibm/power9	3rdparty/open-power-signing-utils: add SecureBoot utility for OpenPOWER	2024-09-06 13:55:50 +00:00
intel	soc/intel/cnvw: Add GPEH Method	2024-10-11 08:32:04 +00:00
mediatek	soc/mt/mt8196/gpio_eint.c: Add assert message	2024-10-02 12:42:32 +00:00
nvidia	arch/arm: Add a few ARM targets as supported by CLANG	2024-08-23 10:40:01 +00:00
qualcomm	soc/qualcomm/sc7{1,2}80: Increase early stages size for clang	2024-10-02 09:18:42 +00:00
rockchip	arch/arm: Add a few ARM targets as supported by CLANG	2024-08-23 10:40:01 +00:00
samsung	tree: Remove blank lines before '}' and after '{'	2024-04-11 19:19:08 +00:00
sifive	tree: Remove duplicated <arch/mmio.h>	2024-08-10 03:35:48 +00:00
ti	soc/ti/am335x: Remove superfluous formats	2024-08-02 14:45:13 +00:00
ucb/riscv	soc: Add SPDX license headers to Kconfig files	2024-02-18 02:03:37 +00:00