f82758a876
This patch updates the Serial IO modes for UART2 to PCI mode in devicetree for glados board. Also we switch over to CONSOLE_SERIAL8250MEM_32 here. 8-bit legacy UART will stop working after devicetree change. BRANCH=None BUG=chrome-os-partner:40857 TEST=Built for glados and tested LPSS logs on glados. CQ-DEPEND=CL:284881 CL:284882 CL:284883 Change-Id: I433979c852c80848c006ef089b43d75a17e761c5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2c37519e0762801cbb9b547b538b385c84299189 Original-Change-Id: I2faec08d089e407c5ab9838bea980553f49821c4 Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284826 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/11002 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> |
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|---|---|---|
| .. | ||
| acpi | ||
| bootblock | ||
| include/soc | ||
| microcode | ||
| romstage | ||
| acpi.c | ||
| chip.c | ||
| chip.h | ||
| cpu.c | ||
| cpu_info.c | ||
| elog.c | ||
| finalize.c | ||
| flash_controller.c | ||
| gpio.c | ||
| igd.c | ||
| Kconfig | ||
| lpc.c | ||
| Makefile.inc | ||
| memmap.c | ||
| monotonic_timer.c | ||
| pch.c | ||
| pcie.c | ||
| pcr.c | ||
| pei_data.c | ||
| pmc.c | ||
| pmutil.c | ||
| ramstage.c | ||
| smbus.c | ||
| smbus_common.c | ||
| smi.c | ||
| smihandler.c | ||
| smmrelocate.c | ||
| systemagent.c | ||
| tsc_freq.c | ||
| uart.c | ||
| xhci.c | ||