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Ronald G. Minnich e6af929661 PIT: memory setup 
Tested and working. Gets us to ramstage.

Change-Id: Ib9ea4a6c912e8152246aaf4f1f084a4aa1626053
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3677
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 21:50:33 +02:00
..
arch armv7a: Enable native memcpy / memset 2013-07-10 21:50:14 +02:00
console ARM: Separate the early console (romstage) from the bootblock console. 2013-07-10 21:47:52 +02:00
cpu PIT: memory setup 2013-07-10 21:50:33 +02:00
device device: Fix spelling 2013-07-10 20:17:25 +02:00
drivers drivers: Fix spelling 2013-07-10 20:18:15 +02:00
ec ec: Reserve correct ioport regions for Chrome OS EC to use 2013-07-10 21:45:11 +02:00
include ARM: Separate the early console (romstage) from the bootblock console. 2013-07-10 21:47:52 +02:00
lib Drop ELF remains from boot code 2013-07-10 21:43:55 +02:00
mainboard PIT: memory setup 2013-07-10 21:50:33 +02:00
northbridge Rename hardwaremain() to main() 2013-07-10 02:40:30 +02:00
southbridge Drop some duplicates of PCI-e config functions 2013-07-10 01:24:42 +02:00
superio w83627hf/acpi: Fix endianess error in floppy drive enumeration code 2013-07-10 02:54:01 +02:00
vendorcode amd/agesa/f15/Lib/amdlib.c: Add missing breaks to switch statement 2013-06-28 01:35:20 +02:00
Kconfig Yabel : Add tracing option needed by i915tool. 2013-06-04 22:57:26 +02:00