coreboot/src/cpu/intel/haswell
Angel Pons cb70d836ed cpu/intel/haswell: Lock PKG_CST_CONFIG_CONTROL MSR
Set PKG_CST_CONFIG_CONTROL MSR bit 15 to make bits 15:0 read-only.

Change-Id: Ieb740aa94255cb3c23a56495c4b645d847637b7f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-15 13:43:05 +00:00
..
acpi.c cpu/intel/haswell/acpi.c: Do not report P_BLK 2021-06-07 04:57:46 +00:00
bootblock.c Add Kconfig TPM 2021-05-26 12:31:10 +00:00
chip.h cpu/intel/haswell: Add s0ix support 2021-01-21 11:27:07 +00:00
finalize.c src: Remove unused <arch/cpu.h> 2021-02-11 10:25:23 +00:00
haswell.h soc/intel/broadwell: Use Haswell CPU headers 2021-01-24 12:03:55 +00:00
haswell_init.c cpu/intel/haswell: Lock PKG_CST_CONFIG_CONTROL MSR 2021-10-15 13:43:05 +00:00
Kconfig src: Introduce ARCH_ALL_STAGES_X86 2021-07-02 08:19:10 +00:00
Makefile.inc cpu/x86/tsc: Deduplicate Makefile logic 2021-09-08 14:35:16 +00:00
romstage.c src: Remove unused <arch/cpu.h> 2021-02-11 10:25:23 +00:00
smmrelocate.c cpu/intel/haswell: Move smmrelocate.c MSR definitions to header 2020-11-03 19:12:01 +00:00