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Vadim Bendebury e1abf87d43 libpayload: improve us timer accuracy
In cases where timer clock frequency is not an integer number of
megahertz, the calculations in timer_us() lack accuracy.

This patch modifies calculations to reduce the error. The maximum
interval this calculation would support decreases, but it still is in
excess of 1844674 seconds for a timer clocked by 10 MHz, which is more
than enough.

BUG=none
TEST=manual
  . verified timer accuracy using a depthcharge CLI command

Change-Id: Iffb323db10e74b0ce3b4d59a56983bfee12e6805
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/207358
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-07-11 01:55:41 +00:00
configs coreboot rush: Add config for serial console 2014-06-11 00:09:41 +00:00
documentation sconfig: rename lapic_cluster -> cpu_cluster 2013-02-14 07:07:20 +01:00
payloads libpayload: improve us timer accuracy 2014-07-11 01:55:41 +00:00
src arm64: 16 byte alignment and ramstage start address 2014-07-11 01:53:04 +00:00
util cbfstool: Remove arch check for different stages 2014-06-26 19:46:54 +00:00
.gitignore rmodules: add support for rmodtool 2014-03-31 22:25:57 +00:00
COMMIT-QUEUE.ini COMMIT-QUEUE.ini: Add documentation. 2013-11-01 14:08:42 +00:00
COPYING update license template. 2006-08-12 22:03:36 +00:00
Makefile coreboot: Introduce stage-specific architecture for coreboot 2014-05-09 04:41:47 +00:00
Makefile.inc vboot2: add verstage 2014-06-30 18:45:04 +00:00
PRESUBMIT.cfg chromeos: Add PRESUBMIT.cfg 2013-05-01 14:31:10 -07:00
README Update README with newer version of the text from the web page 2011-06-15 10:16:33 +02:00
toolchain.inc vboot2: add verstage 2014-06-30 18:45:04 +00:00

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * gcc / g++
 * make

Optional:

 * doxygen (for generating/viewing documentation)
 * iasl (for targets with ACPI support)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.