coreboot/src/vendorcode
Felix Held b65845cb2b vc/amd/fsp/cezanne,mendocino: add FSP CCX CPPC HOB GUID and struct
To generate a complete _CPC ACPI object, coreboot needs the minimal and
nominal core speed values which are specific to the CPU and not only the
CPU family. Since this is done by an undocumented mechanism, FSP has to
do this and puts the information we need into a HOB. This adds the HOB
GUID and the structure of the HOB data.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Change-Id: Ibf338c32de367a3fd57695873da1625338fa196d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66549
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-13 19:28:24 +00:00
..
amd vc/amd/fsp/cezanne,mendocino: add FSP CCX CPPC HOB GUID and struct 2022-08-13 19:28:24 +00:00
cavium rules.h: Use more consistent naming 2022-05-16 21:52:22 +00:00
eltan vc/eltan/security/verified_boot/Makefile: add fmap_config.h dependency 2022-02-22 15:56:03 +00:00
google util/elogtool: Mark redundant boot mode event type as deprecated 2022-08-06 14:06:33 +00:00
intel vc/intel/fsp: Update ADL N FSP headers from v3222.03 to v3267.01 2022-08-07 19:39:43 +00:00
mediatek mb/google: Replace some strings in regulator.c 2022-07-21 10:30:57 +00:00
siemens cbfs: Simplify load/map API names, remove type arguments 2020-12-02 22:13:17 +00:00
Makefile.inc soc/mediatek/mt8192: initialize DRAM using vendor reference code 2021-03-08 03:15:43 +00:00