15a05ab77a
Tested on real hardware, some weirdness remains, probably related to IRQ routing. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@643 f3766cd6-281f-0410-b1cd-43a5c92072e9
55 lines
1.7 KiB
Text
55 lines
1.7 KiB
Text
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/{
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mainboard-vendor = "AMD";
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mainboard-name = "DB800";
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cpus { };
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apic@0 {
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/config/("northbridge/amd/geodelx/apic");
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};
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domain@0 {
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/config/("northbridge/amd/geodelx/domain");
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/* Video RAM has to be in 2MB chunks. */
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geode_video_mb = "8";
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pci@1,0 {
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/config/("northbridge/amd/geodelx/pci");
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};
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pci@15,0 {
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/config/("southbridge/amd/cs5536/dts");
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enable_ide = "1";
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/* Interrupt enables for LPC bus.
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* Each bit is an IRQ 0-15. */
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lpc_serirq_enable = "0x000010da";
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/* LPC IRQ polarity. Each bit is an IRQ 0-15. */
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lpc_serirq_polarity = "0x0000EF25";
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/* 0:continuous 1:quiet */
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lpc_serirq_mode = "1";
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/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none.
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* See virtual PIC spec. */
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enable_gpio_int_route = "0x0D0C0700";
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enable_USBP4_device = "1";
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};
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ioport@46 {
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/config/("superio/winbond/w83627hf/dts");
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com1enable = "1";
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};
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};
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};
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