AMD DB800 support, ported from v2.
Tested on real hardware, some weirdness remains, probably related to IRQ routing. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@643 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Carl-Daniel Hailfinger
parent
aa49b41989
commit
15a05ab77a
8 changed files with 464 additions and 0 deletions
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@ -23,6 +23,18 @@ choice
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prompt "Mainboard model"
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depends on VENDOR_AMD
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config BOARD_AMD_DB800
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bool "DB800"
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select ARCH_X86
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select CPU_AMD_GEODELX
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select OPTION_TABLE
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select NORTHBRIDGE_AMD_GEODELX
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select SOUTHBRIDGE_AMD_CS5536
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select SUPERIO_WINBOND_W83627HF
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select PIRQ_TABLE
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help
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AMD DB800 Geode LX development board.
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config BOARD_AMD_NORWICH
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bool "Norwich"
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select ARCH_X86
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@ -36,5 +48,6 @@ config BOARD_AMD_NORWICH
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endchoice
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source "mainboard/amd/db800/Kconfig"
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source "mainboard/amd/norwich/Kconfig"
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44
mainboard/amd/db800/Kconfig
Normal file
44
mainboard/amd/db800/Kconfig
Normal file
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@ -0,0 +1,44 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007 coresystems GmbH
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## (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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config MAINBOARD_NAME
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string
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default amd/db800
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depends BOARD_AMD_DB800
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help
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This is the default mainboard name.
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config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
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hex
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# TODO: Fix PCI ID.
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default 0x1022
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depends BOARD_AMD_DB800
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help
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Mainboard specific PCI subsystem vendor ID.
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config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
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hex
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# TODO: Fix PCI ID.
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default 0x2323
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depends BOARD_AMD_DB800
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help
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Mainboard specific PCI subsystem device ID.
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34
mainboard/amd/db800/Makefile
Normal file
34
mainboard/amd/db800/Makefile
Normal file
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@ -0,0 +1,34 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2006-2007 coresystems GmbH
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## (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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||||
## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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||||
## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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||||
## along with this program; if not, write to the Free Software
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||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
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INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
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$(src)/northbridge/amd/geodelx/raminit.c \
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$(src)/southbridge/amd/cs5536/smbus_initram.c \
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$(src)/arch/x86/geodelx/geodelx.c
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STAGE2_MAINBOARD_OBJ =
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$(obj)/coreboot.vpd:
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$(Q)printf " BUILD DUMMY VPD\n"
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$(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT)
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74
mainboard/amd/db800/cmos.layout
Normal file
74
mainboard/amd/db800/cmos.layout
Normal file
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@ -0,0 +1,74 @@
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entries
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#start-bit length config config-ID name
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#0 8 r 0 seconds
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#8 8 r 0 alarm_seconds
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#16 8 r 0 minutes
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#24 8 r 0 alarm_minutes
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#32 8 r 0 hours
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#40 8 r 0 alarm_hours
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#48 8 r 0 day_of_week
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#56 8 r 0 day_of_month
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#64 8 r 0 month
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#72 8 r 0 year
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#80 4 r 0 rate_select
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#84 3 r 0 REF_Clock
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#87 1 r 0 UIP
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#88 1 r 0 auto_switch_DST
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#89 1 r 0 24_hour_mode
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#90 1 r 0 binary_values_enable
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#91 1 r 0 square-wave_out_enable
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#92 1 r 0 update_finished_enable
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#93 1 r 0 alarm_interrupt_enable
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#94 1 r 0 periodic_interrupt_enable
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#95 1 r 0 disable_clock_updates
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#96 288 r 0 temporary_filler
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0 384 r 0 reserved_memory
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384 1 e 4 boot_option
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385 1 e 4 last_boot
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386 1 e 1 ECC_memory
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388 4 r 0 reboot_bits
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392 3 e 5 baud_rate
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400 1 e 1 power_on_after_fail
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412 4 e 6 debug_level
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416 4 e 7 boot_first
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420 4 e 7 boot_second
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424 4 e 7 boot_third
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428 4 h 0 boot_index
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432 8 h 0 boot_countdown
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1008 16 h 0 check_sum
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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5 0 115200
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5 1 57600
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5 2 38400
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5 3 19200
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5 4 9600
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5 5 4800
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5 6 2400
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5 7 1200
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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7 0 Network
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7 1 HDD
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7 2 Floppy
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7 8 Fallback_Network
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7 9 Fallback_HDD
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7 10 Fallback_Floppy
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#7 3 ROM
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checksums
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checksum 392 1007 1008
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55
mainboard/amd/db800/dts
Normal file
55
mainboard/amd/db800/dts
Normal file
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@ -0,0 +1,55 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
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||||
* You should have received a copy of the GNU General Public License
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||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/{
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mainboard-vendor = "AMD";
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mainboard-name = "DB800";
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cpus { };
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apic@0 {
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/config/("northbridge/amd/geodelx/apic");
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};
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domain@0 {
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/config/("northbridge/amd/geodelx/domain");
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/* Video RAM has to be in 2MB chunks. */
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geode_video_mb = "8";
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pci@1,0 {
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/config/("northbridge/amd/geodelx/pci");
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};
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pci@15,0 {
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/config/("southbridge/amd/cs5536/dts");
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enable_ide = "1";
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/* Interrupt enables for LPC bus.
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* Each bit is an IRQ 0-15. */
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lpc_serirq_enable = "0x000010da";
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/* LPC IRQ polarity. Each bit is an IRQ 0-15. */
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lpc_serirq_polarity = "0x0000EF25";
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/* 0:continuous 1:quiet */
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lpc_serirq_mode = "1";
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/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none.
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* See virtual PIC spec. */
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enable_gpio_int_route = "0x0D0C0700";
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enable_USBP4_device = "1";
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};
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ioport@46 {
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/config/("superio/winbond/w83627hf/dts");
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com1enable = "1";
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};
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};
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};
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106
mainboard/amd/db800/initram.c
Normal file
106
mainboard/amd/db800/initram.c
Normal file
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@ -0,0 +1,106 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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||||
*
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||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define _MAINOBJECT
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <string.h>
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#include <msr.h>
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#include <io.h>
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#include <amd_geodelx.h>
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#include <northbridge/amd/geodelx/raminit.h>
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/* #include <device/smbus.h>
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* TODO: figure out how smbus functions should be done. See smbus_ops.c
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*/
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extern int smbus_read_byte(u16 device, u8 address);
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#define MANUALCONF 0 /* Do automatic strapped PLL config */
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#define PLLMSRHI 0x00001490 /* manual settings for the PLL */
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#define PLLMSRLO 0x02000030
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#define DIMM0 ((u8) 0xA0)
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#define DIMM1 ((u8) 0xA2)
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u8 spd_read_byte(u16 device, u8 address)
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{
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u8 spdbyte;
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printk(BIOS_DEBUG, "spd_read_byte dev %04x\n", device);
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spdbyte = smbus_read_byte(device, address);
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printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, spdbyte);
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return spdbyte;
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}
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|
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/**
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* Placeholder in case we ever need it. Since this file is a
|
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* template for other motherboards, we want this here and we want the
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* call in the right place.
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*/
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||||
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static void mb_gpio_init(void)
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{
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/* Early mainboard specific GPIO setup */
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}
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|
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/**
|
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* main for initram for the AMD DB800 development platform.
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* It might seem that you could somehow do these functions in, e.g., the cpu
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* code, but the order of operations and what those operations are is VERY
|
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* strongly mainboard dependent. It's best to leave it in the mainboard code.
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*/
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int main(void)
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{
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printk(BIOS_DEBUG, "Hi there from initram (stage1) main!\n");
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post_code(POST_START_OF_MAIN);
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||||
|
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system_preinit();
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||||
printk(BIOS_DEBUG, "done preinit\n");
|
||||
|
||||
mb_gpio_init();
|
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printk(BIOS_DEBUG, "done gpio init\n");
|
||||
|
||||
pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO);
|
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printk(BIOS_DEBUG, "done pll reset\n");
|
||||
|
||||
cpu_reg_init(0, DIMM0, DIMM1);
|
||||
printk(BIOS_DEBUG, "done cpu reg init\n");
|
||||
|
||||
sdram_set_registers();
|
||||
printk(BIOS_DEBUG, "done sdram set registers\n");
|
||||
|
||||
sdram_set_spd_registers(DIMM0, DIMM1);
|
||||
printk(BIOS_DEBUG, "done sdram set spd registers\n");
|
||||
|
||||
sdram_enable(DIMM0, DIMM1);
|
||||
printk(BIOS_DEBUG, "done sdram enable\n");
|
||||
|
||||
/* Check low memory */
|
||||
/*ram_check(0x00000000, 640*1024); */
|
||||
|
||||
printk(BIOS_DEBUG, "stage1 returns\n");
|
||||
return 0;
|
||||
}
|
||||
81
mainboard/amd/db800/irq_tables.h
Normal file
81
mainboard/amd/db800/irq_tables.h
Normal file
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|
@ -0,0 +1,81 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <pirq_routing.h>
|
||||
|
||||
/* Number of slots and devices in the PIR table */
|
||||
#define SLOT_COUNT 4
|
||||
|
||||
/* Platform IRQs */
|
||||
#define PIRQA 10
|
||||
#define PIRQB 11
|
||||
#define PIRQC 10
|
||||
#define PIRQD 11
|
||||
|
||||
/* Map */
|
||||
#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
|
||||
#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
|
||||
#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
|
||||
#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
|
||||
|
||||
/* Link */
|
||||
#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
|
||||
#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
|
||||
#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
|
||||
#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
|
||||
|
||||
/*
|
||||
* AMD DB800 interrupt wiring.
|
||||
*
|
||||
* Devices are:
|
||||
*
|
||||
* FIXME
|
||||
*
|
||||
*/
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE,
|
||||
PIRQ_VERSION,
|
||||
32 + 16 * SLOT_COUNT, /* Max. number of devices on the bus */
|
||||
0x00, /* Where the interrupt router lies (bus) */
|
||||
(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
|
||||
0x00, /* IRQs devoted exclusively to PCI usage */
|
||||
0x100B, /* Vendor */
|
||||
0x002B, /* Device */
|
||||
0, /* Crap (miniport) */
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
|
||||
0x00, /* Checksum */
|
||||
{
|
||||
/* If you change the number of entries, change IRQ_SLOT_COUNT above! */
|
||||
|
||||
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
|
||||
/* CPU */
|
||||
{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
|
||||
|
||||
/* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D. */
|
||||
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},
|
||||
|
||||
/* On-board ethernet */
|
||||
{0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
|
||||
|
||||
/* PCI (slot 1) */
|
||||
{0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x1, 0x0},
|
||||
}
|
||||
};
|
||||
57
mainboard/amd/db800/stage1.c
Normal file
57
mainboard/amd/db800/stage1.c
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <types.h>
|
||||
#include <lib.h>
|
||||
#include <console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <msr.h>
|
||||
#include <io.h>
|
||||
#include <amd_geodelx.h>
|
||||
#include <southbridge/amd/cs5536/cs5536.h>
|
||||
#include <superio/winbond/w83627hf/w83627hf.h>
|
||||
|
||||
#define SERIAL_DEV W83627HF_SP1
|
||||
#define SERIAL_IOBASE 0x3f8
|
||||
|
||||
void hardware_stage1(void)
|
||||
{
|
||||
void w83627hf_enable_serial(u8 dev, u8 serial, u16 iobase);
|
||||
post_code(POST_START_OF_MAIN);
|
||||
geodelx_msr_init();
|
||||
|
||||
cs5536_stage1();
|
||||
|
||||
/* NOTE: must do this AFTER the early_setup!
|
||||
* it is counting on some early MSR setup
|
||||
* for cs5536.
|
||||
*/
|
||||
cs5536_disable_internal_uart();
|
||||
w83627hf_enable_serial(0x2e, SERIAL_DEV, SERIAL_IOBASE);
|
||||
|
||||
}
|
||||
|
||||
void mainboard_pre_payload(void)
|
||||
{
|
||||
geode_pre_payload();
|
||||
banner(BIOS_DEBUG, "mainboard_pre_payload: done");
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue