Nico Huber ee30558c49 soc/intel/skylake: Drop redundant PcieRpEnable ... The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infrastructure instead. Thanks to Nicholas for doing all the mainboard legwork! Change-Id: I2f7e3e1dc6b3d8d6159bd4701e6fd90f4b0f67f4 Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79917 Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2025-04-23 14:15:29 +00:00
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aspire_vn7_572g	soc/intel/skylake: Drop redundant PcieRpEnable	2025-04-23 14:15:29 +00:00
g43t-am3	mb/*/*/early_init.c: Remove unused included southbridge	2024-08-26 02:34:16 +00:00
Kconfig
Kconfig.name	mb/51nb to mb/bytedance: Add SPDX license headers to Kconfig files	2024-02-18 02:00:56 +00:00