Carl-Daniel Hailfinger 4ab20cb518 Move CS5536 IDE configuration into a separate dts and its own PCI device. ... Fix dbe62 IDE/NAND selection. Build-tested on db800, norwich, dbe62, alix.1c, alix.2c3. No additional breakage for dbe61. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://coreboot.org/repository/coreboot-v3@677 f3766cd6-281f-0410-b1cd-43a5c92072e9		2008-05-07 23:21:55 +00:00
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cmos.layout	changes for the mainboards.	2007-06-27 20:38:27 +00:00
dts	Move CS5536 IDE configuration into a separate dts and its own PCI device.	2008-05-07 23:21:55 +00:00
initram.c	Updates to Norwich to boot to Linux. Includes initram updates, IRQ routing, and console output updates.	2008-02-25 17:20:27 +00:00
irq_tables.h	PIRQ table cosmetics/cleanup. Bugfixes and #error for uninitialized	2008-03-07 01:20:36 +00:00
Kconfig	Now version 3: LinuxBIOS -> coreboot rename.	2008-01-27 18:54:57 +00:00
Makefile	Factor out write_pirq_routing_table() for all GeodeLX targets.	2008-03-01 21:33:51 +00:00
stage1.c	Make cs5536_setup_onchipuart() handle both UARTs and add missing break in dbe61 initram.	2008-03-07 06:33:05 +00:00