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Updates to Norwich to boot to Linux. Includes initram updates, IRQ routing, and console output updates.

Browse source 
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@619 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Marc Jones 2008-02-25 17:20:27 +00:00
commit a5b80d49f5
6 changed files with 208 additions and 21 deletions
Download patch file Download diff file Expand all files Collapse all files

1
mainboard/amd/Kconfig
View file

@ -30,6 +30,7 @@ config BOARD_AMD_NORWICH
select OPTION_TABLE
select NORTHBRIDGE_AMD_GEODELX
select SOUTHBRIDGE_AMD_CS5536
select PIRQ_TABLE
help
AMD Norwich Geode LX development board.

2
mainboard/amd/norwich/Makefile
View file

@ -26,7 +26,7 @@ INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/southbridge/amd/cs5536/smbus_initram.c \
$(src)/arch/x86/geodelx/geodelx.c
STAGE2_MAINBOARD_OBJ =
STAGE2_MAINBOARD_OBJ = irq_tables.o
$(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n"

21
mainboard/amd/norwich/dts
View file

@ -20,18 +20,35 @@
/{
mainboard-vendor = "AMD";
mainboard-name = "Norwich";
mainboard-name = "NORWICH";
cpus { };
apic@0 {
/config/("northbridge/amd/geodelx/apic");
};
domain@0 {
/config/("northbridge/amd/geodelx/domain");
/* Video RAM has to be in 2MB chunks. */
geode_video_mb = "8";
pci@1,0 {
/config/("northbridge/amd/geodelx/pci");
};
pci@1,1 {
pci@15,0 {
/config/("southbridge/amd/cs5536/dts");
enable_ide = "1";
/* Interrupt enables for LPC bus.
* Each bit is an IRQ 0-15. */
lpc_serirq_enable = "0x00001002";
/* LPC IRQ polarity. Each bit is an IRQ 0-15. */
lpc_serirq_polarity = "0x0000EFFD";
/* 0:continuous 1:quiet */
lpc_serirq_mode = "1";
/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none.
* See virtual PIC spec. */
enable_gpio_int_route = "0x0D0C0700";
/* COM1 settings */
com1_enable = "1";
com1_address = "0x3f8";
com1_irq = "4";
};
};
};

60
mainboard/amd/norwich/initram.c
View file

@ -31,46 +31,76 @@
#include <amd_geodelx.h>
#include <northbridge/amd/geodelx/raminit.h>
#define MANUALCONF 0 /* Do automatic strapped PLL config. */
/* #include <device/smbus.h>
* TODO: figure out how smbus functions should be done. See smbus_ops.c
*/
extern int smbus_read_byte(u16 device, u8 address);
#define PLLMSRHI 0x00001490 /* Manual settings for the PLL */
#define MANUALCONF 0 /* Do automatic strapped PLL config */
#define PLLMSRHI 0x00001490 /* manual settings for the PLL */
#define PLLMSRLO 0x02000030
#define DIMM0 ((u8) 0xA0)
#define DIMM1 ((u8) 0xA2)
u8 spd_read_byte(u16 device, u8 address)
{
u8 spdbyte;
printk(BIOS_DEBUG, "spd_read_byte dev %04x\n", device);
spdbyte = smbus_read_byte(device, address);
printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, spdbyte);
return spdbyte;
}
/**
* Placeholder in case we ever need it. Since this file is a template for
* other boards, we want this here and we want the call in the right place.
*/
* Placeholder in case we ever need it. Since this file is a
* template for other motherboards, we want this here and we want the
* call in the right place.
*/
static void mb_gpio_init(void)
{
/* Early mainboard specific GPIO setup */
}
/**
* Main for initram for the AMD Norwich. It might seem that you could somehow
* do these functions in, e.g., the CPU code, but the order of operations and
* what those operations are is VERY strongly mainboard dependent. It's best to
* leave it in the mainboard code.
*/
* main for initram for the AMD Norwich development platform.
* It might seem that you could somehow do these functions in, e.g., the cpu
* code, but the order of operations and what those operations are is VERY
* strongly mainboard dependent. It's best to leave it in the mainboard code.
*/
int main(void)
{
u8 smb_devices[] = { DIMM0, DIMM1 };
printk(BIOS_DEBUG, "Hi there from initram (stage1) main!\n");
post_code(POST_START_OF_MAIN);
system_preinit();
printk(BIOS_DEBUG, "done preinit\n");
mb_gpio_init();
printk(BIOS_DEBUG, "done gpio init\n");
pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO);
printk(BIOS_DEBUG, "done pll reset\n");
cpu_reg_init(0, DIMM0, DIMM1);
printk(BIOS_DEBUG, "done cpu reg init\n");
sdram_set_registers();
printk(BIOS_DEBUG, "done sdram set registers\n");
sdram_set_spd_registers(DIMM0, DIMM1);
printk(BIOS_DEBUG, "done sdram set spd registers\n");
sdram_enable(DIMM0, DIMM1);
printk(BIOS_DEBUG, "done sdram enable\n");
/* Check low memory. */
/* ram_check(0, 640 * 1024); */
/* Check low memory */
/*ram_check(0x00000000, 640*1024); */
printk(BIOS_DEBUG, "stage1 returns\n");
return 0;
}

141
mainboard/amd/norwich/irq_tables.c Normal file
View file

@ -0,0 +1,141 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <types.h>
#include <lib.h>
#include <console.h>
#include <device/device.h>
#include <device/pci.h>
#include <string.h>
#include <msr.h>
#include <io.h>
#include <pirq_routing.h>
#include <amd_geodelx.h>
#include "../../../southbridge/amd/cs5536/cs5536.h"
/* Number of slots and devices in the PIR table */
#define SLOT_COUNT 6
/* Platform IRQs */
#define PIRQA 11
#define PIRQB 10
#define PIRQC 11
#define PIRQD 10
/* Map */
#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
/* Link */
#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
/*
* Norwich interrupt wiring.
*
* Devices are:
*
* 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge (rev 31)
* 00:01.1 Graphics device: Advanced Micro Devices [AMD] Geode LX Graphics
* 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX AES Security Block
* 00:0b.0 slot3
* 00:0c.0 slot4
* 00:0d.0 slot1
* 00:0e.0 slot2
* 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03)
* 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01)
* 00:0f.3 Multimedia audio controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio (rev 01)
* 00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02)
* 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02)
*
*/
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE,
PIRQ_VERSION,
32 + 16 * SLOT_COUNT, /* Max. number of devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
0x00, /* IRQs devoted exclusively to PCI usage */
0x100B, /* Vendor */
0x002B, /* Device */
0, /* Crap (miniport) */
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
0x00, /* Checksum */
{
/* If you change the number of entries, change the IRQ_SLOT_COUNT above! */
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
{0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0}, /* slot1 */
{0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x2, 0x0}, /* slot2 */
{0x00, (0x0B << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x3, 0x0}, /* slot3 */
{0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, /* slot4 */
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
int i, j, k, num_entries;
unsigned char pirq[4];
u16 chipset_irq_map;
u32 pciAddr, pirtable_end;
struct irq_routing_table *pirq_tbl;
pirtable_end = copy_pirq_routing_table(addr);
/* Set up chipset IRQ steering. */
pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
printk(BIOS_DEBUG, "%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
chipset_irq_map);
outl(pciAddr & ~3, 0xCF8);
outl(chipset_irq_map, 0xCFC);
pirq_tbl = (struct irq_routing_table *) (addr);
num_entries = (pirq_tbl->size - 32) / 16;
/* Set PCI IRQs. */
for (i = 0; i < num_entries; i++) {
printk(BIOS_DEBUG, "PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
for (j = 0; j < 4; j++) {
printk(BIOS_DEBUG, "INT: %c bitmap: %x ", 'A' + j,
pirq_tbl->slots[i].irq[j].bitmap);
/* Finds lsb in bitmap to IRQ#. */
for (k = 0;
(!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1))
&& (pirq_tbl->slots[i].irq[j].bitmap != 0);
k++);
pirq[j] = k;
printk(BIOS_DEBUG, "PIRQ: %d\n", k);
}
/* Bus, device, slots IRQs for {A,B,C,D}. */
pci_assign_irqs(pirq_tbl->slots[i].bus,
pirq_tbl->slots[i].devfn >> 3, pirq);
}
/* Put the PIR table in memory and checksum. */
return pirtable_end;
}

4
mainboard/amd/norwich/stage1.c
View file

@ -40,9 +40,7 @@ void hardware_stage1(void)
/*
* NOTE: Must do this AFTER the early_setup! It is counting on some
* early MSR setup for the CS5536. We do this early for debug.
* Real setup should be done in chipset init via Config.lb.
*
* TODO: Drop Config.lb reference, update comment.
* Real setup should be done in chipset init via dts settings.
*/
cs5536_setup_onchipuart();
}