ca358e2acc
Total FIFO length is split into many 512 byte blocks, because the max packet size in coreboot is 512 byte, then allot these blocks to GRXFSIZ and GNPTXFSZ evenly. This method avoids the hardcoding and make the FIFO size value work for dwc2 controller that has different FIFO ram size. BUG=chrome-os-partner:32634 BRANCH=None TEST=Boot kernel from USB Change-Id: Ib50a08c193f7f65392810ca3528a97554f2c3999 Signed-off-by: huang lin <hl@rock-chips.com> Reviewed-on: https://chromium-review.googlesource.com/233119 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/242156 Tested-by: Julius Werner <jwerner@chromium.org> Commit-Queue: Julius Werner <jwerner@chromium.org> |
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| .. | ||
| serial | ||
| storage | ||
| timer | ||
| usb | ||
| video | ||
| cbmem_console.c | ||
| hid.c | ||
| keyboard.c | ||
| Makefile.inc | ||
| nvram.c | ||
| options.c | ||
| pci.c | ||
| speaker.c | ||