26d6da4533
Correct UART1 TX/RX pad configuration in early_gpio.c from NF2 to NF1. This enables proper UART1 signaling on GPP_D17 and GPP_D18 when operating in native mode. This change is based on guidance from Intel Doc. No. 648094. TEST=Patched and booted board. Confirmed UART1 communication works via serial adapter. Loopback test passed. Change-Id: Ib1f5ee17e6f3d8a845d024e6b8593606b0430b6f Signed-off-by: Kun-Yi Chen <kunyi.chen@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/88195 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
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