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Varun Upadhyay cd4af952e7 mb/google/ocelot/var/ocelot: Update DDR5 memory configs 
This change updates memory configuration for DDR5 boards based
on board ID.
1. Set SaGv frequencies
2. Configure gear settings
3. Map Channel/PHY clock

TEST: Build ocelot image and boot board with DDR5 memory config.

Change-Id: Iffff1f1ac9b886f58304c002defbc008d3c6bbb8
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89519
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-10-24 21:34:58 +00:00
..
acpi acpi: Move most of HEST ACPI table to common code 2025-09-30 23:52:09 +00:00
arch tree: Use boolean for s3resume 2025-10-23 13:34:15 +00:00
commonlib commonlib/endian: Silence GCC -Warray-bounds false positives 2025-10-20 04:49:43 +00:00
console console: Fix flushing for slow consoles 2025-10-02 22:44:46 +00:00
cpu cpu/x86/topology: Add tile and die ID CPU topology fields 2025-10-13 17:09:18 +00:00
device device: Introduce reworked azalia verb table 2025-09-28 18:18:14 +00:00
drivers drivers/intel/touch: Change I2C speed type to i2c_speed enum 2025-10-24 21:34:48 +00:00
ec ec/starlabs/merlin: Remove the fast charge option 2025-10-24 07:47:15 +00:00
include tree: Use boolean for s3resume 2025-10-23 13:34:15 +00:00
lib tree: Use boolean for s3resume 2025-10-23 13:34:15 +00:00
mainboard mb/google/ocelot/var/ocelot: Update DDR5 memory configs 2025-10-24 21:34:58 +00:00
northbridge tree: Use boolean for s3resume 2025-10-23 13:34:15 +00:00
sbom
security tree: Use boolean for s3resume 2025-10-23 13:34:15 +00:00
soc drivers/intel/touch: Change I2C speed type to i2c_speed enum 2025-10-24 21:34:48 +00:00
southbridge tree: Use boolean for s3resume 2025-10-23 13:34:15 +00:00
superio
vendorcode vc/intel/fsp: Update PTL FSP headers to FSP 3373_03 2025-10-23 15:10:19 +00:00
Kconfig