cc0a410ff5
SoCs with dptx_v2 (such as MT8196) use a different eDP MAC design from old SoCs with dptx_v1. The formulas for register calculation are different: - The horizontal blanking (REG_3160_DP_ENCODER0_P0) is hsync + hbp + hfp on MT8196, while on older SoCs it is hsync + hbp. - The vertical blanking (REG_3174_DP_ENCODER0_P0) is vsync + vbp + vfp on MT8196, but vsync + vbp on earlier SoCs. The current formula for MT8196 only works correctly when ha/va are multiples of 4 and hfp/vfp are 0. The new formula fixes display errors at resolutions like 1366x768 (ha=1366, hfp=48). To distinguish these differences, an edp_version parameter is added. Also update the following settings for correct configuration: - Set AUX_RX_UI_CNT_THR_AUX_FOR_26M to 14 to correct the previous incorrect setting. - Fix DVO_TGEN_H1 calculation for the case where ha is not a multiple of 4 (such as 1366). BUG=b:400886838 BRANCH=rauru TEST=Check the display function on Navi Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com> Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com> Change-Id: Id0ae6845ce6a06cdcbc3dd9b1f8a63e2890c3b24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/88188 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> |
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