f13b4ca285
On Xeon Skylake-SP with dual sockets the platforms make use of 46bit of the address space. Most of the PCI BARs reside in high MMIO, not reachable by x86_32 coreboot. Add support for x86_64 coreboot and confirm that all supported boards are booting without errors. This is done by: - converting all occurrences of VOID * to UINT32 to make sure that FSP UPDs do not change when pointers are 8byte wide. - Drop SetupStructPtr as it's unused within FSP and coreboot TEST: Booted on ocp/tiogapass to Linux. No errors were observed. Change-Id: I8adac99e7600a708b596fd74b00669f4cb4e041b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> |
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| .. | ||
| deltalake | ||
| tiogapass | ||
| Kconfig | ||
| Kconfig.name | ||