coreboot/src/soc
Lijian Zhao 6a09eee4ad soc/intel/cannonlake: Add platform.asl
Include common platform.asl to have generic indication of power
transition state of system.

TEST=Enter and resume from S3, check the post code had been changed to
0096 and 0097.

Change-Id: Ic38ac6d7e60441caeba5c088c9dbe4d901355782
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22111
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-10-20 20:52:46 +00:00
..
amd soc/amd/common: Set AltImageBasePtr to 0 2017-10-20 17:48:56 +00:00
broadcom/cygnus mb/*/*: Remove rtc nvram configurable baud rate 2017-09-23 11:06:25 +00:00
dmp/vortex86ex soc/dmp/vortex86: Fix CMOS read and random RTC reset 2017-08-01 13:20:15 +00:00
imgtec/pistachio mb/*/*: Remove rtc nvram configurable baud rate 2017-09-23 11:06:25 +00:00
intel soc/intel/cannonlake: Add platform.asl 2017-10-20 20:52:46 +00:00
lowrisc/lowrisc soc/lowrisc: Place CBMEM at top of autodetected RAM 2016-12-06 18:51:13 +01:00
marvell/mvmap2315 Update files with no newline at the end 2017-07-24 15:08:16 +00:00
mediatek/mt8173 mb/*/*: Remove rtc nvram configurable baud rate 2017-09-23 11:06:25 +00:00
nvidia mb/*/*: Remove rtc nvram configurable baud rate 2017-09-23 11:06:25 +00:00
qualcomm mb/*/*: Remove rtc nvram configurable baud rate 2017-09-23 11:06:25 +00:00
rockchip include/device: Split i2c.h into three 2017-08-18 15:33:29 +00:00
samsung mb/*/*: Remove rtc nvram configurable baud rate 2017-09-23 11:06:25 +00:00
ucb/riscv soc/ucb/riscv: Place CBMEM at top of autodetected RAM 2016-12-06 18:48:28 +01:00