coreboot/src
Lijian Zhao c866f878bc intel/cannonlake_rvp: Update board name
Change the board name from cannonlake U DDR4 to U LPDDR4 to match
actual platform.

TEST=NONE

Change-Id: Id350e3cbc299d49431197ef5f914ea9a7310a0a5
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-10-20 20:52:50 +00:00
..
acpi src/acpi: Add guards on all header files 2017-08-01 23:04:27 +00:00
arch arch/x86: restore forwarding table on resume for EARLY_EBDA_INIT 2017-10-18 19:56:21 +00:00
commonlib arch/x86: restore forwarding table on resume for EARLY_EBDA_INIT 2017-10-18 19:56:21 +00:00
console console: Ignore loglevel in nvram until ramstage 2017-09-25 13:35:29 +00:00
cpu cpu/amd: Fix spelling of *implementation* 2017-10-16 02:05:16 +00:00
device src/device: Update LTR configuration scheme 2017-10-13 15:21:48 +00:00
drivers elog: Support logging S0ix sleep/wake info in elog 2017-10-19 00:42:49 +00:00
ec google/chromeec: Do not set wake mask before logging EC events 2017-10-19 00:44:31 +00:00
include cpu/x86: add AMD registers to SMM save state 2017-10-19 15:13:18 +00:00
lib drivers/elog: Fix debug build errors 2017-10-16 16:10:51 +00:00
mainboard intel/cannonlake_rvp: Update board name 2017-10-20 20:52:50 +00:00
northbridge nb/sandybridge: Add a kconfig option to ignore XMP max DIMMs 2017-10-19 15:06:13 +00:00
soc soc/intel/cannonlake: Add platform.asl 2017-10-20 20:52:46 +00:00
southbridge sb/intel/bd82x6x: Add new USB currents 2017-10-19 15:07:16 +00:00
superio winbond/w83627hf: Drop early_init.c 2017-09-21 15:40:49 +00:00
vboot vboot: Exclude platform specific files from RW cbfs 2017-10-12 18:33:42 +00:00
vendorcode vendorcode/amd/pi/00670F00: Remove S3 restore functions 2017-10-20 17:49:02 +00:00
Kconfig Enable time stamp collection by default on x86 2017-10-19 09:10:49 +00:00