c7f0697867
On AMD server systems there are multiple PCI root bridges. The root bridge scanning in UEFI Payload is not sufficient to detect the memory and I/O apertures properly. For example on Turin system, the I/O aperture on the first root bridge containing the FCH may not have any I/O resources detected on the PCI devices. This results in the I/O decoding to be disabled on the root bridge, effectively breaking the I/O based serial ports, e.g. on Super I/Os and BMCs. Add new CBMEM ID to report the PCI root bridge aperture information to the payload. The intention is to use the Universal Payload PCI Root Bridges Info HOB that is already supported in the UEFI Payload. The HOB will take priority over the root bridge scanning and properly report the apertures of the PCI root bridges on AMD system. Change-Id: If7f7dc6710f389884adfd292bc5ce77e0c37766f Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> |
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| .. | ||
| bsd | ||
| include/commonlib | ||
| storage | ||
| device_tree.c | ||
| fsp_relocate.c | ||
| iobuf.c | ||
| list.c | ||
| Makefile.mk | ||
| mem_pool.c | ||
| rational.c | ||
| region.c | ||
| sort.c | ||