Julius Werner c230585f43 rk3288: Increase PD_BUS_ACLK (SRAM clock) to improve boot speed ... This patch doubles the ACLK peripheral clock for the PD_BUS power domain to 297MHz, which is the closest to the maximum of 300MHz we can reach by dividing GPLL. This frequency directly translates into SRAM speed, so maximizing it has a huge impact on boot speed (especially with the lack of SRAM caching). BUG=chrome-os-partner:32987 TEST=Booted Veyron_Pinky. Hacked timestamps into vboot and confirmed that the (visibly) long signature verification times are nearly halved. Change-Id: I3f19eaa3d97dcc6235d820c71eb5edf2ae87d647 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/224524 Trybot-Ready: Doug Anderson <dianders@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org>		2014-12-09 21:10:23 +00:00
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imgtec	CBFS: Automate ROM image layout and remove hardcoded offsets	2014-12-03 06:09:54 +00:00
intel	broadwell: Fix incorrect SATA port map mask	2014-12-06 02:34:32 +00:00
marvell	CBFS: Automate ROM image layout and remove hardcoded offsets	2014-12-03 06:09:54 +00:00
nvidia	t132: Add I2S1 support to funit	2014-12-09 02:07:07 +00:00
qualcomm	storm: add ipq8064 blobs to the CBFS	2014-12-09 02:07:12 +00:00
rockchip	rk3288: Increase PD_BUS_ACLK (SRAM clock) to improve boot speed	2014-12-09 21:10:23 +00:00
samsung	CBFS: Automate ROM image layout and remove hardcoded offsets	2014-12-03 06:09:54 +00:00
Kconfig	cosmos: add template for soc and board files	2014-10-09 20:44:46 +00:00
Makefile.inc	cosmos: add template for soc and board files	2014-10-09 20:44:46 +00:00