Andrey Petrov bfea4e98b3 UPSTREAM: soc/intel/apollolake: Let CSE know Ring Buffer Protocol is not needed ... On Apollolake CSE can be used to fetch firmware from boot media. However, when this feature is not used, CSE needs to be explicitly notified of it before memory training is complete. This way it can transition to next state. BUG=chrome-os-partner:53876 TEST=CSE can be power-gated during S0iX. Confirmed with LTB. BUG=None BRANCH=None TEST=None Change-Id: I5141bff350b6c0bb662424b7b709f0787ec5fd28 Original-Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Original-Reviewed-on: https://review.coreboot.org/15494 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/358594 Reviewed-by: Martin Roth <martinroth@chromium.org>		2016-07-07 01:09:28 -07:00
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apollolake	UPSTREAM: soc/intel/apollolake: Let CSE know Ring Buffer Protocol is not needed	2016-07-07 01:09:28 -07:00
baytrail	UPSTREAM: intel romstage: Use run_ramstage()	2016-06-30 10:08:18 -07:00
braswell	soc/intel: indicate to build system that XIP_ROM_SIZE isn't used	2016-05-06 16:50:00 +02:00
broadwell	UPSTREAM: intel romstage: Use run_ramstage()	2016-06-30 10:08:18 -07:00
common	UPSTREAM: skylake: Generate ACPI timing values for I2C devices	2016-07-07 01:08:46 -07:00
fsp_baytrail	UPSTREAM: intel romstage: Use run_ramstage()	2016-06-30 10:08:18 -07:00
fsp_broadwell_de	UPSTREAM: fsp_broadwell_de: Enable Super I/O address range decode	2016-07-01 11:02:47 -07:00
quark	UPSTREAM: soc/intel/quark: Add C bootblock	2016-06-13 15:56:07 -07:00
sch	UPSTREAM: intel/sch: Merge northbridge and southbridge in src/soc	2016-05-20 17:08:20 -07:00
skylake	UPSTREAM: soc/intel/skylake: Add function for gpio_t to ACPI pin translation	2016-07-07 01:09:12 -07:00