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UPSTREAM: soc/intel/apollolake: Let CSE know Ring Buffer Protocol is not needed

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On Apollolake CSE can be used to fetch firmware from boot media. However,
when this feature is not used, CSE needs to be explicitly notified of it
before memory training is complete. This way it can transition to next
state.

BUG=chrome-os-partner:53876
TEST=CSE can be power-gated during S0iX. Confirmed with LTB.

BUG=None
BRANCH=None
TEST=None

Change-Id: I5141bff350b6c0bb662424b7b709f0787ec5fd28
Original-Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15494
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358594
Reviewed-by: Martin Roth <martinroth@chromium.org>
This commit is contained in:
Andrey Petrov 2016-06-28 17:37:09 -07:00 • committed by chrome-bot
commit bfea4e98b3
1 changed files with 8 additions and 0 deletions
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8
src/soc/intel/apollolake/romstage.c
View file

@ -241,6 +241,14 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd)
} else
printk(BIOS_DEBUG, "MRC cache was not found\n");
}
/*
* Tell CSE we do not need to use Ring Buffer Protocol (RBP) to fetch
* firmware for us if we are using memory-mapped SPI. This lets CSE
* state machine transition to next boot state, so that it can function
* as designed.
*/
mupd->FspmConfig.SkipCseRbp = IS_ENABLED(CONFIG_SPI_FLASH_MEMORY_MAPPED);
}
__attribute__ ((weak))