coreboot/src/northbridge
Marcelo Povoa b81b1bb51a agesa: Add support for soldered down DDR3 initialization
Creates a new CONFIG_DDR3_SOLDERED_DOWN variable to enable
handling proper DDR3 SPD initialization. This patch is from
SageBIOS (forked coreboot) sources and is required for platforms
such as the GizmoSphere Gizmo board.

BUG=None
BRANCH=none
TEST=Run on Gizmo board and check SPD dump being same as SageBIOS
Signed-off-by: Marcelo Povoa <marcelogp@chromium.org>

Change-Id: I28e69d649252f542eb3d20d51ff8af69ae6e394a
Reviewed-on: https://chromium-review.googlesource.com/188273
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Marcelo Póvoa <marcelogp@chromium.org>
Commit-Queue: Marcelo Póvoa <marcelogp@chromium.org>
2014-03-05 01:47:18 +00:00
..
amd agesa: Add support for soldered down DDR3 initialization 2014-03-05 01:47:18 +00:00
intel haswell: Allow overriding PRE_GRAPHICS_DELAY in config 2014-02-12 03:48:39 +00:00
rdc GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« 2013-03-01 10:16:08 +01:00
via Rename hardwaremain() to main() 2013-05-10 11:55:20 -07:00
Kconfig Add the support for RDC R8610 Northbridge 2012-03-27 18:37:57 +02:00
Makefile.inc Add the support for RDC R8610 Northbridge 2012-03-27 18:37:57 +02:00