Rename hardwaremain() to main()

... and drop the wrapper on ARMv7

BUG=none
TEST=boot tested on snow
BRANCH=none

Change-Id: Ib2b4315b664292653f8cb898fc5633fce421deca
Reviewed-on: https://gerrit.chromium.org/gerrit/50728
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>

src/arch/x86/lib/c_start.S

@@ -77,7 +77,7 @@ _start:
 #if CONFIG_GDB_WAIT
 	call gdb_stub_breakpoint
 #endif
-	call	hardwaremain
+	call	main
 	/* NOTREACHED */
 .Lhlt:
 	post_code(POST_DEAD_CODE)	/* post ee */

src/include/bootstate.h

@@ -165,7 +165,7 @@ void boot_state_current_block(void);
 void boot_state_current_unblock(void);
 
 /* Entry into the boot state machine. */
-void hardwaremain(void);
+void main(void);
 
 /* In order to schedule boot state callbacks at compile-time specify the
  * entries in an array using the BOOT_STATE_INIT_ENTRIES and

src/include/console/post_codes.h

@@ -83,16 +83,16 @@
 #define POST_ENTRY_C_START			0x13
 
 /**
- * \brief Pre call to hardwaremain()
+ * \brief Pre call to ram stage main()
  *
- * POSTed right before hardwaremain is called from c_start.S
+ * POSTed right before ram stage main() is called from c_start.S
  */
 #define POST_PRE_HARDWAREMAIN			0x79
 
 /**
- * \brief Entry into coreboot in hardwaremain (RAM)
+ * \brief Entry into coreboot in ram stage main()
  *
- * This is the first call in hardwaremain.c. If this code is POSTed, then
+ * This is the first call in ram stage main(). If this code is POSTed, then
  * ramstage has succesfully loaded and started executing.
  */
 #define POST_ENTRY_RAMSTAGE			0x80

src/lib/hardwaremain.c

@@ -444,7 +444,7 @@ static void boot_state_schedule_static_entries(void)
 	}
 }
 
-void hardwaremain(void)
+void main(void)
 {
 	timestamp_stash(TS_START_RAMSTAGE);
 	post_code(POST_ENTRY_RAMSTAGE);

src/lib/timestamp.c

@@ -92,7 +92,7 @@ static int timestamp_entries CAR_GLOBAL = 0;
  * This is needed when time stamping before the CBMEM area
  * is initialized. The function timestamp_sync() is used to
  * write the time stamps to the CBMEM area. This is done in
- * hardwaremain()
+ * ram stage main()
  */
 
 void timestamp_stash(enum timestamp_id id)

src/mainboard/amd/dinar/get_bus_conf.c

@@ -83,7 +83,7 @@ void get_bus_conf(void)
 	 * call.  The logically correct place to call AmdInitLate is after PCI scan is done,
 	 * after the decision about S3 resume is made, and before the system tables are
 	 * written into RAM.  The routine that is responsible for writing the tables is
-	 * "write_tables", called near the end of "hardwaremain".  There is no platform
+	 * "write_tables", called near the end of "main".  There is no platform
 	 * specific entry point between the S3 resume decision point and the call to
 	 * "write_tables", and the next platform specific entry points are the calls to
 	 * the ACPI table write functions.  The first of ose would seem to be the right

src/mainboard/amd/inagua/get_bus_conf.c

@@ -71,7 +71,7 @@ void get_bus_conf(void)
 	 * call.  The logically correct place to call AmdInitLate is after PCI scan is done,
 	 * after the decision about S3 resume is made, and before the system tables are
 	 * written into RAM.  The routine that is responsible for writing the tables is
-	 * "write_tables", called near the end of "hardwaremain".  There is no platform
+	 * "write_tables", called near the end of "main".  There is no platform
 	 * specific entry point between the S3 resume decision point and the call to
 	 * "write_tables", and the next platform specific entry points are the calls to
 	 * the ACPI table write functions.  The first of ose would seem to be the right

src/mainboard/amd/parmer/get_bus_conf.c

@@ -69,7 +69,7 @@ void get_bus_conf(void)
 	 * call.  The logically correct place to call AmdInitLate is after PCI scan is done,
 	 * after the decision about S3 resume is made, and before the system tables are
 	 * written into RAM.  The routine that is responsible for writing the tables is
-	 * "write_tables", called near the end of "hardwaremain".  There is no platform
+	 * "write_tables", called near the end of "main".  There is no platform
 	 * specific entry point between the S3 resume decision point and the call to
 	 * "write_tables", and the next platform specific entry points are the calls to
 	 * the ACPI table write functions.  The first of ose would seem to be the right

src/mainboard/amd/persimmon/get_bus_conf.c

@@ -74,7 +74,7 @@ void get_bus_conf(void)
  * call.	The logically correct place to call AmdInitLate is after PCI scan is done,
  * after the decision about S3 resume is made, and before the system tables are
  * written into RAM.	The routine that is responsible for writing the tables is
- * "write_tables", called near the end of "hardwaremain".	There is no platform
+ * "write_tables", called near the end of "main".	There is no platform
  * specific entry point between the S3 resume decision point and the call to
  * "write_tables", and the next platform specific entry points are the calls to
  * the ACPI table write functions.	The first of ose would seem to be the right

src/mainboard/amd/south_station/get_bus_conf.c

@@ -71,7 +71,7 @@ void get_bus_conf(void)
  * call.  The logically correct place to call AmdInitLate is after PCI scan is done,
  * after the decision about S3 resume is made, and before the system tables are
  * written into RAM.  The routine that is responsible for writing the tables is
- * "write_tables", called near the end of "hardwaremain".  There is no platform
+ * "write_tables", called near the end of "main".  There is no platform
  * specific entry point between the S3 resume decision point and the call to
  * "write_tables", and the next platform specific entry points are the calls to
  * the ACPI table write functions.  The first of ose would seem to be the right

src/mainboard/amd/thatcher/get_bus_conf.c

@@ -69,7 +69,7 @@ void get_bus_conf(void)
 	 * call.  The logically correct place to call AmdInitLate is after PCI scan is done,
 	 * after the decision about S3 resume is made, and before the system tables are
 	 * written into RAM.  The routine that is responsible for writing the tables is
-	 * "write_tables", called near the end of "hardwaremain".  There is no platform
+	 * "write_tables", called near the end of "main".  There is no platform
 	 * specific entry point between the S3 resume decision point and the call to
 	 * "write_tables", and the next platform specific entry points are the calls to
 	 * the ACPI table write functions.  The first of ose would seem to be the right

src/mainboard/amd/torpedo/get_bus_conf.c

@@ -76,7 +76,7 @@ void get_bus_conf(void)
  * call.  The logically correct place to call AmdInitLate is after PCI scan is done,
  * after the decision about S3 resume is made, and before the system tables are
  * written into RAM.  The routine that is responsible for writing the tables is
- * "write_tables", called near the end of "hardwaremain".  There is no platform
+ * "write_tables", called near the end of "main".  There is no platform
  * specific entry point between the S3 resume decision point and the call to
  * "write_tables", and the next platform specific entry points are the calls to
  * the ACPI table write functions.  The first of ose would seem to be the right

src/mainboard/amd/union_station/get_bus_conf.c

@@ -71,7 +71,7 @@ void get_bus_conf(void)
  * call.  The logically correct place to call AmdInitLate is after PCI scan is done,
  * after the decision about S3 resume is made, and before the system tables are
  * written into RAM.  The routine that is responsible for writing the tables is
- * "write_tables", called near the end of "hardwaremain".  There is no platform
+ * "write_tables", called near the end of "main".  There is no platform
  * specific entry point between the S3 resume decision point and the call to
  * "write_tables", and the next platform specific entry points are the calls to
  * the ACPI table write functions.  The first of ose would seem to be the right

src/mainboard/asrock/e350m1/get_bus_conf.c

@@ -71,7 +71,7 @@ void get_bus_conf(void)
  * call.  The logically correct place to call AmdInitLate is after PCI scan is done,
  * after the decision about S3 resume is made, and before the system tables are
  * written into RAM.  The routine that is responsible for writing the tables is
- * "write_tables", called near the end of "hardwaremain".  There is no platform
+ * "write_tables", called near the end of "main".  There is no platform
  * specific entry point between the S3 resume decision point and the call to
  * "write_tables", and the next platform specific entry points are the calls to
  * the ACPI table write functions.  The first of ose would seem to be the right

src/mainboard/asus/f2a85-m/get_bus_conf.c

@@ -69,7 +69,7 @@ void get_bus_conf(void)
 	 * call.  The logically correct place to call AmdInitLate is after PCI scan is done,
 	 * after the decision about S3 resume is made, and before the system tables are
 	 * written into RAM.  The routine that is responsible for writing the tables is
-	 * "write_tables", called near the end of "hardwaremain".  There is no platform
+	 * "write_tables", called near the end of "main".  There is no platform
 	 * specific entry point between the S3 resume decision point and the call to
 	 * "write_tables", and the next platform specific entry points are the calls to
 	 * the ACPI table write functions.  The first of ose would seem to be the right

src/mainboard/emulation/qemu-armv7/Makefile.inc

@@ -13,7 +13,6 @@
 ## GNU General Public License for more details.
 
 romstage-y += romstage.c
-ramstage-y += ramstage.c
 
 bootblock-y += media.c
 romstage-y += media.c

src/mainboard/emulation/qemu-armv7/ramstage.c

@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-void hardwaremain(void);
-void main(void)
-{
-	hardwaremain();
-}

src/mainboard/google/snow/Makefile.inc

@@ -25,5 +25,4 @@ romstage-y += wakeup.c
 
 # ramstage-y += ec.c
 ramstage-y += mainboard.c
-ramstage-y += ramstage.c
 ramstage-y += chromeos.c

src/mainboard/google/snow/ramstage.c

@@ -1,24 +0,0 @@
-/*
- * Copyright (C) 2013 The ChromeOS Authors
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-void hardwaremain(void);
-void main(void)
-{
-	hardwaremain();
-}

src/mainboard/lippert/frontrunner-af/get_bus_conf.c

@@ -74,7 +74,7 @@ void get_bus_conf(void)
  * call.	The logically correct place to call AmdInitLate is after PCI scan is done,
  * after the decision about S3 resume is made, and before the system tables are
  * written into RAM.	The routine that is responsible for writing the tables is
- * "write_tables", called near the end of "hardwaremain".	There is no platform
+ * "write_tables", called near the end of "main".	There is no platform
  * specific entry point between the S3 resume decision point and the call to
  * "write_tables", and the next platform specific entry points are the calls to
  * the ACPI table write functions.	The first of ose would seem to be the right

src/mainboard/lippert/toucan-af/get_bus_conf.c

@@ -74,7 +74,7 @@ void get_bus_conf(void)
  * call.	The logically correct place to call AmdInitLate is after PCI scan is done,
  * after the decision about S3 resume is made, and before the system tables are
  * written into RAM.	The routine that is responsible for writing the tables is
- * "write_tables", called near the end of "hardwaremain".	There is no platform
+ * "write_tables", called near the end of "main".	There is no platform
  * specific entry point between the S3 resume decision point and the call to
  * "write_tables", and the next platform specific entry points are the calls to
  * the ACPI table write functions.	The first of ose would seem to be the right

src/mainboard/supermicro/h8qgi/get_bus_conf.c

@@ -63,7 +63,7 @@ void get_bus_conf(void)
 	 * call.  The logically correct place to call AmdInitLate is after PCI scan is done,
 	 * after the decision about S3 resume is made, and before the system tables are
 	 * written into RAM.  The routine that is responsible for writing the tables is
-	 * "write_tables", called near the end of "hardwaremain".  There is no platform
+	 * "write_tables", called near the end of "main".  There is no platform
 	 * specific entry point between the S3 resume decision point and the call to
 	 * "write_tables", and the next platform specific entry points are the calls to
 	 * the ACPI table write functions.  The first of ose would seem to be the right

src/mainboard/supermicro/h8scm/get_bus_conf.c

@@ -63,7 +63,7 @@ void get_bus_conf(void)
 	 * call.  The logically correct place to call AmdInitLate is after PCI scan is done,
 	 * after the decision about S3 resume is made, and before the system tables are
 	 * written into RAM.  The routine that is responsible for writing the tables is
-	 * "write_tables", called near the end of "hardwaremain".  There is no platform
+	 * "write_tables", called near the end of "main".  There is no platform
 	 * specific entry point between the S3 resume decision point and the call to
 	 * "write_tables", and the next platform specific entry points are the calls to
 	 * the ACPI table write functions.  The first of ose would seem to be the right

src/mainboard/tyan/s8226/get_bus_conf.c

@@ -63,7 +63,7 @@ void get_bus_conf(void)
 	 * call.  The logically correct place to call AmdInitLate is after PCI scan is done,
 	 * after the decision about S3 resume is made, and before the system tables are
 	 * written into RAM.  The routine that is responsible for writing the tables is
-	 * "write_tables", called near the end of "hardwaremain".  There is no platform
+	 * "write_tables", called near the end of "main".  There is no platform
 	 * specific entry point between the S3 resume decision point and the call to
 	 * "write_tables", and the next platform specific entry points are the calls to
 	 * the ACPI table write functions.  The first of ose would seem to be the right

src/northbridge/via/vx800/examples/chipset_init.c

@@ -604,7 +604,7 @@ void init_VIA_chipset(void)
  *	In the dev_enumerate() phase,
  */
 
-void hardwaremain(void)
+void main(void)
 {
 	struct lb_memory *lb_mem;
 #if CONFIG_HAVE_ACPI_RESUME