coreboot/include
Marc Jones b6c89edb04 Improve the setup of MTRRs in stage1 to handle alignment and power of
2 size calculations.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1133 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-02-15 18:12:34 +00:00
..
arch/x86 Improve the setup of MTRRs in stage1 to handle alignment and power of 2009-02-15 18:12:34 +00:00
device
console.h
elf.h
elf_boot.h
globalvars.h
ip_checksum.h
isa-dma.h
keyboard.h
lar.h
lib.h
mc146818rtc.h
post_code.h
shared.h
spd.h
spd_ddr2.h
spinlock.h
string.h
tables.h
uart8250.h