Improve the setup of MTRRs in stage1 to handle alignment and power of
2 size calculations. Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1133 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Marc Jones
parent
54d59cf82c
commit
b6c89edb04
3 changed files with 162 additions and 49 deletions
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@ -38,6 +38,9 @@
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void set_mtrr_ram_access(void)
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{
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struct msr msr;
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u8 mtrr_reg;
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u32 mem_sizek;
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u32 mem_basek;
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disable_cache();
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@ -68,20 +71,31 @@ void set_mtrr_ram_access(void)
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stage1_set_fix_mtrr(MTRRfix4K_F8000_MSR,
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MTRR_READ_MEM | MTRR_WRITE_MEM | MTRR_TYPE_WRBACK);
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/* 1MB - TOM */
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/* 0MB - TOM */
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/* The fixed MTRRS will override 0MB-1MB but because the size needs to
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* be power of two aligned we want the base to be power of two aligned(0).
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* Otherwise we will use all the MTRRs up.
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*/
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msr = rdmsr(TOP_MEM);
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stage1_set_var_mtrr_x(0, 0x00100000, 0x0, msr.lo, msr.hi, MTRR_TYPE_WRBACK);
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mem_sizek = stage1_resk((msr.hi << 32) | msr.lo);
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mem_basek = 0x0;
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mtrr_reg = 0;
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mtrr_reg = stage1_range_to_mtrr(mtrr_reg, mem_basek, mem_sizek,
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MTRR_TYPE_WRBACK, CPU_ADDR_BITS);
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/* System ROM (Assume 1MB) */
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stage1_set_var_mtrr(1, 0xFFFFFFFF - (u32)((CONFIG_COREBOOT_ROMSIZE_KB << 10) - 1),
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CONFIG_COREBOOT_ROMSIZE_KB << 10, MTRR_TYPE_WRTHROUGH);
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mtrr_reg = stage1_range_to_mtrr(mtrr_reg,
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(u32)(0xFFFFFFFF >> 10) - (u32)(CONFIG_COREBOOT_ROMSIZE_KB - 1),
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CONFIG_COREBOOT_ROMSIZE_KB, MTRR_TYPE_WRBACK, CPU_ADDR_BITS);
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/* 4GB - TOM2 */
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msr = rdmsr(SYSCFG_MSR);
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if (msr.lo & SYSCFG_MSR_TOM2En) {
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msr = rdmsr(TOP_MEM2);
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stage1_set_var_mtrr_x(2, 0x0, 0x00000001, msr.lo, msr.hi,
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MTRR_TYPE_WRBACK);
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mem_sizek = stage1_resk((msr.hi << 32) | msr.lo);
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mem_basek = (0xFFFFFFFF >> 10) + 1; /* 4GB */
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mtrr_reg = stage1_range_to_mtrr(mtrr_reg, mem_basek, mem_sizek,
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MTRR_TYPE_WRBACK, CPU_ADDR_BITS);
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}
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/* Enable Fixed and Variable MTRRs MSRs*/
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@ -14,49 +14,49 @@
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#include <msr.h>
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#include <mtrr.h>
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void disable_var_mtrr(unsigned int reg)
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#if 1
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#define BIOS_MTRRS 6
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#define OS_MTRRS 2
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#else
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#define BIOS_MTRRS 8
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#define OS_MTRRS 0
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#endif
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#define MTRRS (BIOS_MTRRS + OS_MTRRS)
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/* fms: find most sigificant bit set, stolen from Linux Kernel Source. */
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static inline u32 fms(u32 x)
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{
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/* The invalid bit is kept in the mask so we simply
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* clear the relevent mask register to disable a
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* range.
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*/
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struct msr zero;
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zero.lo = zero.hi = 0;
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wrmsr(MTRRphysMask_MSR(reg), zero);
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int r;
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__asm__("bsrl %1,%0\n\t"
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"jnz 1f\n\t"
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"movl $0,%0\n"
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"1:" : "=r" (r) : "g" (x));
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return r;
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}
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void stage1_set_var_mtrr(
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unsigned long reg, unsigned long base, unsigned long size, unsigned long type)
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/* fls: find least sigificant bit set */
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static inline u32 fls(u32 x)
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{
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/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
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/* FIXME: It only support 4G less range */
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struct msr basem, maskm;
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basem.lo = base | type;
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basem.hi = 0;
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wrmsr(MTRRphysBase_MSR(reg), basem);
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maskm.lo = ~(size - 1) | 0x800;
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maskm.hi = (1<<(CPU_ADDR_BITS-32))-1;
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wrmsr(MTRRphysMask_MSR(reg), maskm);
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int r;
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__asm__("bsfl %1,%0\n\t"
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"jnz 1f\n\t"
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"movl $32,%0\n"
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"1:" : "=r" (r) : "g" (x));
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return r;
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}
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void stage1_set_var_mtrr_x(
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unsigned long reg, u32 base_lo, u32 base_hi, u32 size_lo, u32 size_hi, unsigned long type)
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u32 stage1_resk(u64 value)
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{
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/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
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struct msr basem, maskm;
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basem.lo = (base_lo & 0xfffff000) | type;
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basem.hi = base_hi & ((1<<(CPU_ADDR_BITS-32))-1);
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wrmsr(MTRRphysBase_MSR(reg), basem);
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maskm.hi = (1<<(CPU_ADDR_BITS-32))-1;
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if(size_lo) {
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maskm.lo = ~(size_lo - 1) | 0x800;
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} else {
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maskm.lo = 0x800;
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maskm.hi &= ~(size_hi - 1);
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u32 resultk;
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if (value < (1ULL << 42)) {
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resultk = value >> 10;
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}
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wrmsr(MTRRphysMask_MSR(reg), maskm);
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else {
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resultk = 0xffffffff;
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}
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return resultk;
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}
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/* Sets the entire fixed mtrr to a cache type. */
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@ -77,14 +77,114 @@ void stage1_set_fix_mtrr(u32 reg, u8 type)
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msr = rdmsr(SYSCFG_MSR);
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msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
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wrmsr(SYSCFG_MSR, msr);
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}
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/* Set a variable MTRR, comes from linux kernel source
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* use stage1_range_to_mtrr() to set variable MTRRs.
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*/
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static void stage1_set_var_mtrr(u8 reg, u32 basek, u32 sizek,
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u8 type, u32 address_bits)
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{
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struct msr base, mask;
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u32 address_mask_high;
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if (reg >= MTRRS) {
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printk(BIOS_ERR,"Requested MTRR is out of range!\n");
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return;
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}
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if (sizek == 0) {
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struct msr zero;
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zero.lo = zero.hi = 0;
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disable_cache(); /* disable/enable cache when setting MTRRs */
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/* The invalid bit is kept in the mask, so we simply clear the
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relevant mask register to disable a range. */
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wrmsr (MTRRphysMask_MSR(reg), zero);
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enable_cache();
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return;
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}
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address_mask_high = ((1u << (address_bits - 32u)) - 1u);
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base.hi = basek >> 22;
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base.lo = basek << 10;
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printk(BIOS_SPEW, "ADDRESS_MASK_HIGH=%#x\n", address_mask_high);
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if (sizek < 4*1024*1024) {
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mask.hi = address_mask_high;
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mask.lo = ~((sizek << 10) -1);
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}
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else {
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mask.hi = address_mask_high & (~((sizek >> 22) -1));
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mask.lo = 0;
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}
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disable_cache(); /* disable/enable cache when setting MTRRs */
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/* Bit 32-35 of MTRRphysMask should be set to 1 */
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base.lo |= type;
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mask.lo |= 0x800;
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wrmsr (MTRRphysBase_MSR(reg), base);
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wrmsr (MTRRphysMask_MSR(reg), mask);
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enable_cache();
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}
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/* Set a memory range to variable MTRRs.
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* This handles the power of 2 alignment requirement.
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*/
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u8 stage1_range_to_mtrr(u8 reg, u32 range_startk, u32 range_sizek,
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u8 type, u32 address_bits)
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{
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if (!range_sizek) {
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printk(BIOS_SPEW, "Zero-sized MTRR range @%dKB\n", range_startk);
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return reg;
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}
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if (reg >= BIOS_MTRRS) {
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printk(BIOS_ERR, "ERROR: Out of MTRRs for base: %4dMB, range: %dMB, type %s\n",
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range_startk >>10, range_sizek >> 10,
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(type==MTRR_TYPE_UNCACHEABLE)?"UC":
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((type==MTRR_TYPE_WRBACK)?"WB":"Other") );
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return reg;
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}
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while(range_sizek) {
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u32 max_align, align;
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u32 sizek;
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/* Compute the maximum size I can make a range */
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max_align = fls(range_startk);
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align = fms(range_sizek);
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if (align > max_align) {
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align = max_align;
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}
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sizek = 1 << align;
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printk(BIOS_DEBUG,"Setting variable MTRR %d, base: %dKB, range: %dKB, type %s\n",
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reg, range_startk, sizek,
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(type==MTRR_TYPE_UNCACHEABLE)?"UC":
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((type==MTRR_TYPE_WRBACK)?"WB":"Other")
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);
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stage1_set_var_mtrr(reg++, range_startk, sizek, type, address_bits);
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range_startk += sizek;
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range_sizek -= sizek;
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if (reg >= BIOS_MTRRS) {
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printk(BIOS_ERR, "Out of variable MTRRs!\n");
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break;
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}
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}
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return reg;
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}
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void cache_cbmem(int type)
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{
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/* Enable caching for 0 - 1MB using variable mtrr */
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/* Enable caching for 0 - 1MB(CONFIG_CBMEMK) using variable mtrr */
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disable_cache();
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stage1_set_var_mtrr(0, 0x00000000, CONFIG_CBMEMK << 10, type);
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stage1_range_to_mtrr(0, 0, CONFIG_CBMEMK, MTRR_TYPE_WRBACK, CPU_ADDR_BITS);
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enable_cache();
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}
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@ -119,7 +219,8 @@ void do_early_mtrr_init(const unsigned long *mtrr_msrs)
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/* enable write through caching so we can do execute in place
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* on the flash rom.
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*/
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stage1_set_var_mtrr(1, XIP_ROM_BASE, XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
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stage1_range_to_mtrr(1, 0, XIP_ROM_BASE >> 10, XIP_ROM_SIZE >> 10,
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MTRR_TYPE_WRBACK, CPU_ADDR_BITS);
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#endif
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#endif
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@ -35,12 +35,10 @@
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void x86_setup_var_mtrrs(unsigned address_bits);
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void x86_setup_mtrrs(unsigned address_bits);
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int x86_mtrr_check(void);
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void stage1_set_var_mtrr(unsigned long reg, unsigned long base,
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unsigned long size, unsigned long type);
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void stage1_set_fix_mtrr(u32 reg, u8 type);
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void stage1_set_var_mtrr_x(unsigned long reg, u32 base_lo, u32 base_hi,
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u32 size_lo, u32 size_hi, unsigned long type);
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u8 stage1_range_to_mtrr(u8 reg, u32 range_startk, u32 range_sizek,
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u8 type, u32 address_bits);
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u32 stage1_resk(u64 value);
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#endif
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