Sean Rhodes b03f85f3a2 soc/intel/tigerlake: Change the maximum C state to C8 ... The EDS says that Tiger Lake "supports C0, C2, C3, C6, C8, and C10 package states". Update the highest state for non-S0ix boards accordingly. Change-Id: I3fe0f5a8f9b52a44d1951037d74df4a244ba602e Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86199 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2025-01-29 11:45:25 +00:00
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acpi	acpi: Guard CBMEM driver against Chrome devices	2025-01-16 16:12:19 +00:00
arch	arch/x86: Replace 'unsigned long int' by 'unsigned long'	2025-01-08 02:57:44 +00:00
commonlib	commonlib: Add new "ESE completed AUnit loading" TS	2025-01-26 16:58:58 +00:00
console
cpu	cpu/x86/smm: Fix smm_get_save_state() returning invalid pointer	2025-01-20 03:25:41 +00:00
device	device: Fix debug print	2025-01-08 08:18:55 +00:00
drivers	drivers/amd/opensil/romstage.c: Implement cbmem_top_chipset in driver	2025-01-28 20:18:29 +00:00
ec	ec/dasharo: Add dependancy to EC_DASHARO_EC_FLASH_SIZE	2025-01-28 09:44:47 +00:00
include	soc/intel/common: Add Panther Lake DTT support	2025-01-26 16:57:49 +00:00
lib	lib: Replace 'unsigned long int' by 'unsigned long'	2025-01-12 04:51:51 +00:00
mainboard	mb/starlabs/starfighter: Disable SATA	2025-01-29 11:44:16 +00:00
northbridge	haswell NRI: Post-process selected timings	2024-12-10 09:38:00 +00:00
sbom
security	drivers/pc80/tpm: Remove flag TPM_RDRESP_NEED_DELAY	2024-10-14 15:26:11 +00:00
soc	soc/intel/tigerlake: Change the maximum C state to C8	2025-01-29 11:45:25 +00:00
southbridge	sb/intel/bd82x6x: Apply EHCI mapping to xhci_overcurrent_mapping	2025-01-21 05:01:14 +00:00
superio	superio/ite: Add support for IT8625E	2024-11-21 15:49:12 +00:00
vendorcode	drivers/amd/opensil/romstage.c: Implement cbmem_top_chipset in driver	2025-01-28 20:18:29 +00:00
Kconfig	drivers/option: Add CBFS file based option backend	2025-01-22 03:25:40 +00:00