Patrick Rudolph 97bf77e52e soc/amd/common/block/lpc: Limit ROM2 to 16MiB ... Don't map more than 16MiB in ROM2 decode window when the SPI ROM size is bigger than 16MiB. TEST: amd/birman+ still boots with bigger SPI flash sizes. Change-Id: Ie811f6a38363f2e900611b3f3f407a94d8137c89 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86582 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2025-03-10 15:21:04 +00:00
..
acpi	src/acpigen: support 0-initialized buffer in acpigen_write_byte_buffer	2025-03-05 16:44:43 +00:00
arch	arch/riscv: Add common FDT build	2025-02-14 17:11:19 +00:00
commonlib	{commonlib, lib}: Rename CBMEM_ID_FSP_LOGO to CBMEM_ID_BMP_LOGO	2025-03-06 19:02:27 +00:00
console
cpu	cpu/intel/haswell: Usee boolean for haswell_is_ult()	2025-03-03 01:15:17 +00:00
device	device/pci_device: Move PCI Option ROM code into pci_rom.c	2025-03-10 11:35:57 +00:00
drivers	{drivers, lib}: Move low-battery user notification logic outside FSP	2025-03-08 07:17:32 +00:00
ec	ec/google/chromeec/acpi: Add support for Body Detect	2025-03-10 07:55:56 +00:00
include	soc/intel/cannonlake: Let coreboot lock MSR_IA32_DEBUG_INTERFACE	2025-03-10 15:19:26 +00:00
lib	{drivers, lib}: Move low-battery user notification logic outside FSP	2025-03-08 07:17:32 +00:00
mainboard	mb/google/brya/var/anahera: add memory NT6AP512T32BL-J1	2025-03-10 15:18:17 +00:00
northbridge	haswell NRI: Do sense amplifier offset training	2025-03-08 22:55:39 +00:00
sbom
security
soc	soc/amd/common/block/lpc: Limit ROM2 to 16MiB	2025-03-10 15:21:04 +00:00
southbridge	haswell NRI: Add DDR3 JEDEC reset and init	2025-03-08 22:53:24 +00:00
superio
vendorcode	soc/intel/xeon-sp/spr: Hook up public FSP bin and headers	2025-03-10 08:08:48 +00:00
Kconfig	Kconfig: Update prompt and help text for CBFS_SIZE	2025-03-01 23:29:09 +00:00