Lijian Zhao ae4eee17dd soc/intel/cannonlake: Remove depreciated UPD selection ... Several FSP silicon init UPD have been moved to memory init stage, modify the coreboot accordingly. The UPDs below are affected: SkipMpInit VtdBaseAddress VtdDisable X2ApicOptOut BUG=N/A TEST=Build pass with FSP revision 7.0.47.50. Change-Id: Ic0416dcd9ea1fe063cdd0c2f27257cd4cb4ba7e8 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/29260 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2018-11-05 09:04:32 +00:00
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amd	soc/amd/stoneyridge: Fix get_cpu_count()	2018-10-31 22:00:03 +00:00
broadcom	src: Add missing include <stdint.h>	2018-11-01 11:25:07 +00:00
cavium	src: Add missing include <stdint.h>	2018-11-01 11:25:07 +00:00
imgtec	soc/imgtech/pistachio: Convert to board_reset()	2018-10-22 08:34:33 +00:00
intel	soc/intel/cannonlake: Remove depreciated UPD selection	2018-11-05 09:04:32 +00:00
mediatek	mediatek/mt8183: Add AUXADC driver	2018-11-02 19:57:47 +00:00
nvidia	src: Add missing include <stdint.h>	2018-11-01 11:25:07 +00:00
qualcomm	src: Add missing include <stdint.h>	2018-11-01 11:25:07 +00:00
rockchip	src: Add missing include <stdint.h>	2018-10-30 09:41:08 +00:00
samsung	src: Remove unneeded whitespace	2018-10-23 15:52:09 +00:00
sifive	riscv: add support smp_pause / smp_resume	2018-11-05 09:03:40 +00:00
ucb	riscv: add support smp_pause / smp_resume	2018-11-05 09:03:40 +00:00