Lijian Zhao ae4eee17dd soc/intel/cannonlake: Remove depreciated UPD selection ... Several FSP silicon init UPD have been moved to memory init stage, modify the coreboot accordingly. The UPDs below are affected: SkipMpInit VtdBaseAddress VtdDisable X2ApicOptOut BUG=N/A TEST=Build pass with FSP revision 7.0.47.50. Change-Id: Ic0416dcd9ea1fe063cdd0c2f27257cd4cb4ba7e8 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/29260 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2018-11-05 09:04:32 +00:00
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acpi
arch	riscv: add support for supervisor binary interface (SBI)	2018-11-05 09:04:01 +00:00
commonlib	src: Remove unneeded whitespace	2018-10-23 15:52:09 +00:00
console	console: Set default loglevel to 8 (SPEW) for CONFIG_CHROMEOS	2018-10-18 12:50:41 +00:00
cpu	amd: Fix non-local header treated as local	2018-11-05 09:00:26 +00:00
device	src: Remove unneeded whitespace	2018-10-23 15:52:09 +00:00
drivers	amd: Fix non-local header treated as local	2018-11-05 09:00:26 +00:00
ec	ec/google/wilco: Add wake pin configuration	2018-11-02 16:07:01 +00:00
include	src: Add missing include <stdint.h>	2018-11-01 11:25:07 +00:00
lib	reset: Finalize move to new API	2018-10-31 15:29:42 +00:00
mainboard	mb/google/poppy/variant/nocturne: add Nanya memory option	2018-11-05 09:03:11 +00:00
northbridge	amd: Fix non-local header treated as local	2018-11-05 09:00:26 +00:00
security	src: Add missing include <stdint.h>	2018-11-01 11:25:07 +00:00
soc	soc/intel/cannonlake: Remove depreciated UPD selection	2018-11-05 09:04:32 +00:00
southbridge	amd: Fix non-local header treated as local	2018-11-05 09:00:26 +00:00
superio	src: Add missing include <stdint.h>	2018-11-01 11:25:07 +00:00
vendorcode	sb/intel/lynxpoint: Include <stdint.h> to fix compilation errors	2018-11-01 22:24:24 +00:00
Kconfig	reset: Finalize move to new API	2018-10-31 15:29:42 +00:00