Nick Vaccaro ace29dff9e lp4x: Add new memory parts and generate SPDs ... Add MT53D512M64D4NW-046 WT:F memory part to LP4x global list of available LP4x parts and to the global JSON file containing LP4x parts and their characteristics. BUG=b:172993397 TEST=none Change-Id: I09c6eab640c169dbdb451964967d14a31e314496 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>		2020-11-30 08:03:35 +00:00
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alderlake	soc/intel: Configure P2SB before other PCH controllers	2020-11-29 17:18:02 +00:00
apollolake	soc/intel/block/pmc: Only include the PCI driver when it is not hidden	2020-11-22 22:25:03 +00:00
baytrail	src: Include <arch/io.h> when appropriate	2020-10-26 06:44:40 +00:00
braswell	soc/intel/braswell/bootblock/bootblock.c: Report the FSP-T output	2020-11-22 22:17:53 +00:00
broadwell	soc/intel/{broadwell,quark}: Drop PEI_DATA typedef	2020-11-25 09:15:36 +00:00
cannonlake	soc/intel: Configure P2SB before other PCH controllers	2020-11-29 17:18:02 +00:00
common	soc/intel/block/pmclib.c: Properly guard apm_control()	2020-11-22 22:25:23 +00:00
denverton_ns	soc/intel/denverton_ns: Hook up SMMSTORE	2020-11-23 12:43:17 +00:00
elkhartlake	soc/intel: Configure P2SB before other PCH controllers	2020-11-29 17:18:02 +00:00
icelake	soc/intel: Configure P2SB before other PCH controllers	2020-11-29 17:18:02 +00:00
jasperlake	soc/intel: Configure P2SB before other PCH controllers	2020-11-29 17:18:02 +00:00
quark	soc/intel/{broadwell,quark}: Drop PEI_DATA typedef	2020-11-25 09:15:36 +00:00
skylake	soc/intel: Configure P2SB before other PCH controllers	2020-11-29 17:18:02 +00:00
tigerlake	lp4x: Add new memory parts and generate SPDs	2020-11-30 08:03:35 +00:00
xeon_sp	soc/intel/xeon_sp: Enable SMI handler	2020-11-24 12:44:28 +00:00
Kconfig	fsp2_0: Gather Kconfig declarations	2020-04-05 23:26:24 +00:00