coreboot/src/soc/intel
Ben Gardner 2d3d1b7eee baytrail: add C0 and D0 stepping decode
The E3800 with ordering code FH8065301487717 is stepping D0, value 0x11.
Add that so the debug log shows 'D0' instead of '??'.

Also, add the C0 stepping decode to fsp_baytrail.

Change-Id: Ibec764fcf5d3f448e38831786a071f5ab6066d67
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: http://review.coreboot.org/12488
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-21 03:41:34 +01:00
..
baytrail baytrail: add C0 and D0 stepping decode 2015-11-21 03:41:34 +01:00
braswell tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
broadwell tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
common intel: Add MMA feature in coreboot 2015-11-20 18:21:25 +01:00
fsp_baytrail baytrail: add C0 and D0 stepping decode 2015-11-21 03:41:34 +01:00
skylake intel/skylake: Fix flash_controller.c compilation 2015-11-20 20:22:34 +01:00