coreboot/src/soc
Ben Gardner 2d3d1b7eee baytrail: add C0 and D0 stepping decode
The E3800 with ordering code FH8065301487717 is stepping D0, value 0x11.
Add that so the debug log shows 'D0' instead of '??'.

Also, add the C0 stepping decode to fsp_baytrail.

Change-Id: Ibec764fcf5d3f448e38831786a071f5ab6066d67
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: http://review.coreboot.org/12488
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-21 03:41:34 +01:00
..
broadcom/cygnus arm/arm64: Generalize bootblock C entry point 2015-11-11 05:08:07 +01:00
imgtec/pistachio tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
intel baytrail: add C0 and D0 stepping decode 2015-11-21 03:41:34 +01:00
marvell/bg4cd arm/arm64: Generalize bootblock C entry point 2015-11-11 05:08:07 +01:00
nvidia arm64: tegra132: tegra210: Remove old arm64/stage_entry.S 2015-11-17 21:31:20 +01:00
qualcomm/ipq806x tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
rockchip/rk3288 google/veyron*: Pulse the i2c clock once if sda was low 2015-11-18 16:29:16 +01:00
samsung tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
ucb/riscv tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00