Patrick Rudolph 5af2deae92 nb/intel/sandybridge/raminit: Fix SMBIOS 17 bus width ... The bus width has to be encoded where the lower 3 bits are the bus width in multiple of 8 and the following two bits give the error checking bits in multiple of 8. Hardcode to 64 bit as done on haswell. TODO: Make it dynamic once there's ECC support. Change-Id: I3b83a098205455b1c820d0436c6984938f261466 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>		2018-07-26 14:12:02 +00:00
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e7505	nb/intel/e7505: Leave ROM as un-cacheable in postcar	2018-06-20 19:00:07 +00:00
fsp_rangeley	src/northbridge: Use "foo *bar" instead of "foo* bar"	2018-07-09 09:29:53 +00:00
fsp_sandybridge	src/northbridge: Use "foo *bar" instead of "foo* bar"	2018-07-09 09:29:53 +00:00
gm45	src/northbridge: Use "foo *bar" instead of "foo* bar"	2018-07-09 09:29:53 +00:00
haswell	src/nb: Fix non-local header treated as local	2018-07-02 07:39:16 +00:00
i440bx	nb/intel/i440bx: Switch to POSTCAR_STAGE	2018-06-17 19:17:11 +00:00
i945	nb/i945/raminit: Correct C0DRAMW & C1DRAMW for 4 DIMMs	2018-07-12 11:52:52 +00:00
nehalem	nb/intel/nehalem: Remove the C native graphic init	2018-07-26 11:35:59 +00:00
pineview	src/northbridge: Use "foo *bar" instead of "foo* bar"	2018-07-09 09:29:53 +00:00
sandybridge	nb/intel/sandybridge/raminit: Fix SMBIOS 17 bus width	2018-07-26 14:12:02 +00:00
x4x	sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables	2018-06-29 07:45:30 +00:00