Patrick Rudolph 5af2deae92 nb/intel/sandybridge/raminit: Fix SMBIOS 17 bus width ... The bus width has to be encoded where the lower 3 bits are the bus width in multiple of 8 and the following two bits give the error checking bits in multiple of 8. Hardcode to 64 bit as done on haswell. TODO: Make it dynamic once there's ECC support. Change-Id: I3b83a098205455b1c820d0436c6984938f261466 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>		2018-07-26 14:12:02 +00:00
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amd	AGESA binaryPI: Remove code for CONFIG_CBB!=0	2018-07-23 08:02:23 +00:00
intel	nb/intel/sandybridge/raminit: Fix SMBIOS 17 bus width	2018-07-26 14:12:02 +00:00
via/vx900	src/northbridge: Use "foo *bar" instead of "foo* bar"	2018-07-09 09:29:53 +00:00