coreboot/src/southbridge
Subrata Banik df052ff30e soc/intel: Extend CSE RW Update and ME read access for payload sync
Modify the dependencies for `SOC_INTEL_CSE_RW_UPDATE` and
`ME_REGION_ALLOW_CPU_READ_ACCESS` config options to include
`SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD`.

This allows these features to be enabled even when CSE sync is performed
in the payload, not just within coreboot (when `SOC_INTEL_CSE_LITE_SKU`
config is enabled).

BUG=b:305898363
TEST=Builds and boots successfully:
    * google/rex0 with SOC_INTEL_CSE_LITE_SKU
    * google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD

Change-Id: Id6ec19d74237f278e8383c89923523871b2cc2db
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-07-11 15:24:07 +00:00
..
amd util/amdfwtool: build amdfwtool only for all tools or AMD CPUs 2024-02-26 14:50:18 +00:00
intel soc/intel: Extend CSE RW Update and ME read access for payload sync 2024-07-11 15:24:07 +00:00
ricoh/rl5c476 tree: Remove blank lines before '}' and after '{' 2024-04-11 19:19:08 +00:00
ti tree: Remove blank lines before '}' and after '{' 2024-04-11 19:19:08 +00:00