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coreboot/src/cpu
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david 56f2f3bff0 haswell: Update microcode revision 
CPUID 306C3 Haswell MOB C-0 microcode to 1ch
CPUID 40651 Haswell ULT C-0 microcode to 1ch

BUG=none
BRANCH=peppy
TEST=manual: build and boot on peppy and check microcode revision
localhost ~ # grep microcode /proc/cpuinfo
microcode       : 0x1c
microcode       : 0x1c

Change-Id: I1a4c21c81c5dc08dfbb296e133f5677887bd7877
Signed-off-by: David Wu <David_Wu@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/210031
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: David Wu <david_wu@quantatw.com>
Tested-by: David Wu <david_wu@quantatw.com>
2014-07-29 04:37:18 +00:00
..
amd coreboot: Introduce stage-specific architecture for coreboot 2014-05-09 04:41:47 +00:00
armltd coreboot: Introduce stage-specific architecture for coreboot 2014-05-09 04:41:47 +00:00
intel haswell: Update microcode revision 2014-07-29 04:37:18 +00:00
via coreboot: Introduce stage-specific architecture for coreboot 2014-05-09 04:41:47 +00:00
x86 coreboot classes: Add dynamic classes to coreboot 2014-07-28 19:19:34 +00:00
Kconfig coreboot: Move ARCH_* from board/Kconfig to cpu or soc Kconfig. 2014-05-08 22:36:06 +00:00
Makefile.inc coreboot: Introduce stage-specific architecture for coreboot 2014-05-09 04:41:47 +00:00