Xiang Wang a5b265bb0c riscv: separately define stack locations at different stages ... BOOTBLOCK/ROMSTAGE run in CAR/scratchpad. When RAMSTAGE begins execution will enable cache, then CAR will disappear. So the Stack will be separated. Change-Id: I37a0c1928052cabf61ba5c25b440363b75726782 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/28383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>		2018-09-02 03:10:58 +00:00
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arch	riscv: separately define stack locations at different stages	2018-09-02 03:10:58 +00:00
bits.h	riscv-trap-handling: Add preliminary trap handling for riscv	2015-08-26 23:50:45 +00:00
mcall.h	riscv: add include/arch/smp/ directory	2018-07-12 11:53:30 +00:00
stdint.h	riscv: update the definition of intptr_t/uintptr_t	2018-08-30 14:48:26 +00:00
vm.h	arch/riscv: Store mprv bit in size_t	2018-04-26 11:50:20 +00:00