Xiang Wang a5b265bb0c riscv: separately define stack locations at different stages ... BOOTBLOCK/ROMSTAGE run in CAR/scratchpad. When RAMSTAGE begins execution will enable cache, then CAR will disappear. So the Stack will be separated. Change-Id: I37a0c1928052cabf61ba5c25b440363b75726782 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/28383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>		2018-09-02 03:10:58 +00:00
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acpi
arch	riscv: separately define stack locations at different stages	2018-09-02 03:10:58 +00:00
commonlib	cbtable: remove chromeos_acpi from cbtable	2018-08-22 15:33:50 +00:00
console
cpu	cpu/intel/common: add function to init cppc_config	2018-08-20 15:53:28 +00:00
device	nb/intel/sandybridge/raminit: Move fill_smbios17 to ddr3.c	2018-08-21 23:04:08 +00:00
drivers	src/drivers/spi/tpm: Fix typo & capitalize TPM and IRQ	2018-09-02 03:09:30 +00:00
ec	chromeec: PS2K node can't be under SIO node	2018-09-02 03:08:27 +00:00
include	siemens/mc_apl1: Disable PCI clock outputs on XIO bridge	2018-08-27 06:31:27 +00:00
lib	lib/gpio.c: Validate num_gpio	2018-08-28 15:36:51 +00:00
mainboard	mb/lenovo: dGPU power handling on T430, T530	2018-09-02 03:10:39 +00:00
northbridge	nb/intel/*/gma.c: Skip NGI when VGA decode is not enabled	2018-08-22 18:26:14 +00:00
security	security/tpm: Fix TPM 1.2 state machine issues	2018-08-21 15:45:15 +00:00
soc	riscv: separately define stack locations at different stages	2018-09-02 03:10:58 +00:00
southbridge	intel: Use common HPET table revision function	2018-08-27 15:50:52 +00:00
superio	superio/ite/it8721f: Add SuperIO ACPI declarations	2018-08-21 14:45:36 +00:00
vendorcode	acpi: Hide Chrome and coreboot specific devices	2018-08-28 15:14:42 +00:00
Kconfig