coreboot/src/cpu
Filip Lewiński 04ea4724e2 Makefile.mk: separate bootblocks into BOOTBLOCK and TOPSWAP
Add Kconfig INTEL_TOP_SWAP_SEPARATE_REGIONS. When enabled, place the
regular bootblock in BOOTBLOCK and the Top Swap bootblock in TOPSWAP
to simplify A B updates. This lays groundwork for redundancy where one
bootblock remains a read only golden copy and the other is replaceable.

No swap control logic is added in this change. The option depends on
INTEL_ADD_TOP_SWAP_BOOTBLOCK and defaults to n so existing builds are
unchanged. A custom .fmd is required with BOOTBLOCK and TOPSWAP added
at the end of the image.

Background and update flow are described here:
Link: https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5Y
V35/

TEST=Build and run Protectli VP6650 (ADL-P), boots successfully with
correct microcode

Change-Id: I489406dd8d08ad85bb46324d3d009acb49b6c52a
Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
2025-11-16 18:35:27 +00:00
..
amd treewide: Remove unused CHIPs 2024-02-20 11:01:36 +00:00
armltd arch to cpu: Add SPDX license headers to Kconfig files 2024-02-18 01:58:52 +00:00
intel Makefile.mk: separate bootblocks into BOOTBLOCK and TOPSWAP 2025-11-16 18:35:27 +00:00
power9 include/device/device.h: Remove CHIP_NAME() macro 2024-01-31 09:51:58 +00:00
qemu-power8 include/device/device.h: Remove CHIP_NAME() macro 2024-01-31 09:51:58 +00:00
qemu-x86 cpu/qemu: Enable IDT_IN_EVERY_STAGE 2024-12-17 17:37:54 +00:00
via cpu/via/c7: Compress ramstage with LZ4 by default 2024-11-21 09:26:17 +00:00
x86 cpu/x86/topology: Add tile and die ID CPU topology fields 2025-10-13 17:09:18 +00:00
Kconfig arch to cpu: Add SPDX license headers to Kconfig files 2024-02-18 01:58:52 +00:00
Makefile.mk Revert "src/cpu,soc/amd/common/block/cpu: Add preload_microcode" 2025-04-14 13:55:47 +00:00