coreboot/src
Aaron Durbin 956c4f2d4c x86: link romstage and ramstage with 1 file
To reduce file clutter merge romstage.ld and ramstage.ld
into a single memlayout.ld. The naming is consistent with
other architectures and chipsets for their linker script
names. The cache-as-ram linking rules are put into a separate
file such that other rules can be applied for future verstage
support.

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built rambi and dmp/vortex86ex.

Change-Id: I1e8982a6a28027566ddd42a71b7e24e2397e68d2
Signed-off-by: Aaron Durbin <adubin@chromium.org>
Reviewed-on: http://review.coreboot.org/11521
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09 19:35:42 +00:00
..
acpi acpi/sata: add generic sata ssdt port generator 2015-06-07 01:24:47 +02:00
arch x86: link romstage and ramstage with 1 file 2015-09-09 19:35:42 +00:00
console consoles: remove unused infrastructure 2015-05-26 19:02:54 +02:00
cpu rmodule: use program.ld for linking 2015-09-09 19:35:30 +00:00
device symbols: add '_' to pci_drivers and cpu_drivers symbols 2015-09-05 15:36:23 +00:00
drivers drivers/pc80: Do not initialize PS2 keyboard by default 2015-09-09 16:47:48 +00:00
ec Drop "See file CREDITS..." comment 2015-09-07 15:54:50 +00:00
include rmodule: use program.ld for linking 2015-09-09 19:35:30 +00:00
lib rmodule: use program.ld for linking 2015-09-09 19:35:30 +00:00
mainboard rk3288: Allow board-specific APLL (CPU clock) settings 2015-09-08 11:50:50 +00:00
northbridge x86: bootblock: remove linking and program flow from build system 2015-09-09 03:22:58 +00:00
soc verstage: use common program.ld for linking 2015-09-09 19:35:20 +00:00
southbridge x86: bootblock: remove linking and program flow from build system 2015-09-09 03:22:58 +00:00
superio superio/smsc: Add support for SMSC DME1737 2015-07-13 17:11:00 +02:00
vendorcode verstage: use common program.ld for linking 2015-09-09 19:35:20 +00:00
Kconfig Kconfig: Remove EXPERT mode 2015-08-30 07:50:47 +00:00