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coreboot/src/cpu/intel/haswell
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Patrick Rudolph eee5be070a cpu/intel: Use mtrr_use_temp_range() 
Cover the SPIROM with a temporary MTRR to speed up SPI flash accesses
after MPinit has removed the MTRR that was installed for postcar stage.

TEST=Booted on Lenovo X220 and measured using cbmem -t:
Before:
  16:finished LZMA decompress (ignore for x86)         1,391,520 (366,351)

After:
  16:finished LZMA decompress (ignore for x86)         1,218,418 (210,054)

Boots 156msec faster than before.

Change-Id: Ia3df06b5c2a09e05c76361f3e38be83475122ee7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88811
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-08-19 20:56:12 +00:00
..
acpi.c
bootblock.c
chip.h
finalize.c
haswell.h cpu/intel/haswell: Export PCODE mailbox functions 2025-05-27 15:07:25 +00:00
haswell_init.c cpu/intel: Use mtrr_use_temp_range() 2025-08-19 20:56:12 +00:00
Kconfig arch to cpu: Add SPDX license headers to Kconfig files 2024-02-18 01:58:52 +00:00
Makefile.mk cpu/intel/haswell: Export PCODE mailbox functions 2025-05-27 15:07:25 +00:00
pcode_mailbox.c cpu/intel/haswell: Export PCODE mailbox functions 2025-05-27 15:07:25 +00:00
romstage.c
smmrelocate.c smmrelocate: Drop unused parameter 2025-04-23 21:02:27 +00:00