Ziang Wang c1e0384367 arch/riscv/include: Cast 'id' to int in OTHER_HLS() ... The 'id' in OTHER_HSL macro is non-typed, downflow would occur when ‘id’ is unsigned and less greater than hart_id. Cast it to int. Change-Id: I777337b7e374024aff6fb36de603b799b1a65371 Signed-off-by: Ziang Wang <wangziang.ok@bytedance.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>		2025-09-28 18:16:52 +00:00
..
include	arch/riscv/include: Cast 'id' to int in OTHER_HLS()	2025-09-28 18:16:52 +00:00
arch_timer.c
boot.c	arch/riscv/boot.c: Comment OpenSBI Supervisor mode switch	2024-02-10 17:28:47 +00:00
bootblock.S
fit_payload.c
fp_asm.S
Kconfig	arch/riscv: Add common FDT build	2025-02-14 17:11:19 +00:00
Makefile.mk	tree: Replace scan-build by clang-tidy	2025-07-01 01:12:32 +00:00
mcall.c	arch/riscv: Refactor SMP code	2024-11-28 13:59:34 +00:00
misc.c
opensbi.c	arch/riscv: Remove opensbi submodule includes	2024-07-26 13:05:41 +00:00
payload.c	tree: Drop unused <cbmem.h>	2024-04-12 04:24:03 +00:00
pmp.c	arch/riscv: Add PMP print function	2024-08-11 17:10:45 +00:00
ramstage.S	arch/riscv/ramstage.S: Add comments for passed arguments	2023-11-13 11:09:39 +00:00
romstage.S	arch/riscv/romstage: Start from assembly	2023-11-23 17:50:55 +00:00
sbi.c	arch/riscv: add new SBI calls	2024-03-25 02:47:56 +00:00
smp.c	arch/riscv: Refactor SMP code	2024-11-28 13:59:34 +00:00
tables.c
trap_handler.c	arch/riscv: Remove ram probing	2024-08-20 12:54:12 +00:00
trap_util.S	arch/riscv: Remove ram probing	2024-08-20 12:54:12 +00:00
virtual_memory.c	arch/riscv: remove misaligned load/store/fetch handling	2024-03-27 14:45:06 +00:00