Kenji Chen 8ef55ee996 Broadwell: Revise programming flow for write-once registers ... Extended PCIe Capability and Advanced Error Report locates at offset 0x100 is W/O, and the subsequent write following the 1st write to the register takes no effect. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: d2862b6c1c Original-BUG=chrome-os-partner:31424. Original-TEST=Build a image and check the programming value is correct on Original-Samus. Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Change-Id: I0bed30f516ee0307b4a86cad2f669a18ff4994db Original-Reviewed-on: https://chromium-review.googlesource.com/219985 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I3711aa0f1f918baebb4fd77a3615bdf5956ba844 Reviewed-on: http://review.coreboot.org/9209 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>		2015-04-02 17:27:46 +02:00
..
baytrail	baytrail: Change USB3 PLL VCO and iCLK PLL current on BYT-M/D CPU	2015-04-02 17:27:28 +02:00
broadwell	Broadwell: Revise programming flow for write-once registers	2015-04-02 17:27:46 +02:00
common	bootstate: use structure pointers for scheduling callbacks	2015-03-18 16:41:43 +01:00
fsp_baytrail	intel/fsp_baytrail: Add PCI Root Port IRQ Routing	2015-03-12 20:35:49 +01:00
Kconfig	broadwell: Hook into the build system	2014-12-31 21:23:09 +01:00
Makefile.inc	broadwell: Hook into the build system	2014-12-31 21:23:09 +01:00