Enable FSP 'MultiPhaseSilicon' init to execute tcss configure during silicon init. Type-c aux lines DC bias changes are propagated from tigerlake platform. TEST=Verified superspeed pendrive detection on coldboot. Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com> Change-Id: Ifce6abb0fce20e408931b904426131a42a5a4a36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> |
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| alderlake | ||
| apollolake | ||
| baytrail | ||
| braswell | ||
| broadwell | ||
| cannonlake | ||
| common | ||
| denverton_ns | ||
| elkhartlake | ||
| icelake | ||
| jasperlake | ||
| quark | ||
| skylake | ||
| tigerlake | ||
| xeon_sp | ||
| Kconfig | ||