Deepti Deshatty 8e7facf343 soc/intel/alderlake: mb/intel/sm: Add tcss code ... Enable FSP 'MultiPhaseSilicon' init to execute tcss configure during silicon init. Type-c aux lines DC bias changes are propagated from tigerlake platform. TEST=Verified superspeed pendrive detection on coldboot. Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com> Change-Id: Ifce6abb0fce20e408931b904426131a42a5a4a36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>		2021-05-18 10:09:04 +00:00
..
amd	soc/amd/*/Makefile.inc: Strip the quotes	2021-05-16 22:23:31 +00:00
cavium
example
intel	soc/intel/alderlake: mb/intel/sm: Add tcss code	2021-05-18 10:09:04 +00:00
mediatek	soc/mediatek/mt8195: enable ARM64_USE_ARM_TRUSTED_FIRMWARE	2021-05-18 07:06:52 +00:00
nvidia	cbfs: Replace more instances of cbfs_boot_locate() with newer APIs	2021-03-17 08:10:20 +00:00
qualcomm	Coachz: Observe SPI_CLK voltage level is only 1.4V, need to adjust	2021-04-24 00:24:00 +00:00
rockchip	soc/rockchip/rk3399/sdram: Add channel to error message	2021-03-04 01:22:10 +00:00
samsung	commonlib/region: Turn addrspace_32bit into a more official API	2021-04-21 02:06:26 +00:00
sifive	memlayout: Store region sizes as separate symbols	2021-02-19 08:39:26 +00:00
ti	soc/ti/am335x/mmc.c: Fix memset length argument	2021-04-04 09:58:26 +00:00
ucb