0ef4bd807c
This change updates memory configuration for DDR5. 1. Set SaGv frequencies 2. Configure gear settings 3. Map Channel/PHY clock Bug=b:452542491 TEST=Build kodkod image. Change-Id: I49939c8bde06b4a3148b48307b4ccbebf8ba560d Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com> |
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| .. | ||
| acpi | ||
| arch | ||
| commonlib | ||
| console | ||
| cpu | ||
| device | ||
| drivers | ||
| ec | ||
| include | ||
| lib | ||
| mainboard | ||
| northbridge | ||
| sbom | ||
| security | ||
| soc | ||
| southbridge | ||
| superio | ||
| vendorcode | ||
| Kconfig | ||