Meera Ravindranath 5b3a0ff4f1 soc/intel/jasperlake: Add VR Configuration settings ... This CL fixes the CPU Throttling issue. BUG=b:167472333 TEST=Build and boot dedede and observe the slope and offset values getting updated in the fsp debug log Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I3fa32218040263f0abef8b9dd4c52efb31289fd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>		2020-10-08 19:11:34 +00:00
..
amd	soc/amd/picasso: Remove xhci0_force_gen1 from soc config	2020-10-08 01:30:36 +00:00
cavium	soc/cavium: Drop unneeded empty lines	2020-09-22 17:14:49 +00:00
intel	soc/intel/jasperlake: Add VR Configuration settings	2020-10-08 19:11:34 +00:00
mediatek	soc/mediatek: Add function to raise the CPU frequency of MT8192	2020-10-08 11:58:42 +00:00
nvidia	soc/nvidia: Drop unneeded empty lines	2020-09-22 17:14:59 +00:00
qualcomm	sc7180: Remove LIMITS_CFG loading in romstage.	2020-10-07 22:41:55 +00:00
rockchip	soc/rockchip: Drop unneeded empty lines	2020-09-21 16:18:49 +00:00
samsung	soc/samsung: Drop unneeded empty lines	2020-09-21 16:18:07 +00:00
sifive	include/console/uart: make index parameter unsigned	2020-09-12 14:59:33 +00:00
ti	include/console/uart: make index parameter unsigned	2020-09-12 14:59:33 +00:00
ucb	soc/ucb/riscv: Add chip_operations stub	2020-05-28 09:30:35 +00:00